[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension

[Paolo Savini via Phabricator via llvm-commits]

PaoloS updated this revision to Diff 213913.
PaoloS added a comment.

Fixed typos, bad indentations and capitalization.
Added `uimm6` and `uimm7` riscv asm operand types in order to have more precise classes to represent the templates of the instructions with 5-bit, 6-bit and 7-bit immediate fields. The riscv asm operand `uimm5` already existed.
Added missing `rev` pseudo instructions for riscv64.
Fixed the tests accordingly.
Added comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65649/new/

https://reviews.llvm.org/D65649

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rv32Zbb-invalid.s
  llvm/test/MC/RISCV/rv32Zbb-valid.s
  llvm/test/MC/RISCV/rv32Zbbp-invalid.s
  llvm/test/MC/RISCV/rv32Zbbp-valid.s
  llvm/test/MC/RISCV/rv32Zbc-invalid.s
  llvm/test/MC/RISCV/rv32Zbc-valid.s
  llvm/test/MC/RISCV/rv32Zbe-invalid.s
  llvm/test/MC/RISCV/rv32Zbe-valid.s
  llvm/test/MC/RISCV/rv32Zbp-invalid.s
  llvm/test/MC/RISCV/rv32Zbp-valid.s
  llvm/test/MC/RISCV/rv32Zbr-invalid.s
  llvm/test/MC/RISCV/rv32Zbr-valid.s
  llvm/test/MC/RISCV/rv32Zbs-invalid.s
  llvm/test/MC/RISCV/rv32Zbs-valid.s
  llvm/test/MC/RISCV/rv32Zbt-invalid.s
  llvm/test/MC/RISCV/rv32Zbt-valid.s
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv32bc-invalid.s
  llvm/test/MC/RISCV/rv32bc-valid.s
  llvm/test/MC/RISCV/rv64Zbb-invalid.s
  llvm/test/MC/RISCV/rv64Zbb-valid.s
  llvm/test/MC/RISCV/rv64Zbbp-invalid.s
  llvm/test/MC/RISCV/rv64Zbbp-valid.s
  llvm/test/MC/RISCV/rv64Zbc-invalid.s
  llvm/test/MC/RISCV/rv64Zbc-valid.s
  llvm/test/MC/RISCV/rv64Zbe-invalid.s
  llvm/test/MC/RISCV/rv64Zbe-valid.s
  llvm/test/MC/RISCV/rv64Zbm-invalid.s
  llvm/test/MC/RISCV/rv64Zbm-valid.s
  llvm/test/MC/RISCV/rv64Zbp-invalid.s
  llvm/test/MC/RISCV/rv64Zbp-valid.s
  llvm/test/MC/RISCV/rv64Zbr-invalid.s
  llvm/test/MC/RISCV/rv64Zbr-valid.s
  llvm/test/MC/RISCV/rv64Zbs-invalid.s
  llvm/test/MC/RISCV/rv64Zbs-valid.s
  llvm/test/MC/RISCV/rv64Zbt-invalid.s
  llvm/test/MC/RISCV/rv64Zbt-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s
  llvm/test/MC/RISCV/rv64bc-invalid.s
  llvm/test/MC/RISCV/rv64bc-valid.s

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