[PATCH] D65887: [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: efriedma, tlively, craig.topper, spatel.
Herald added subscribers: sunfish, aheejin, jgravelle-google, sbc100, javed.absar, dschuff.
Herald added a project: LLVM.

This patch attempts to peek through vectors based on the demanded bits/elt of a particular ISD::EXTRACT_VECTOR_ELT node, allowing us to avoid dependencies on ops that have no impact on the extract.

In particular this helps remove some unnecessary scalar->vector->scalar patterns.

@tlively The wasm shift patterns are annoying - we scalarize the vector masking of the shift amounts due to something to do with the promotion of the i16 elements to  i32 - the extractions from the <8 x i16> create i32 scalars with undefined upper bits. A hack would be to only do this if we don't have implicit extension/truncation - what do you think?


Repository:
  rL LLVM

https://reviews.llvm.org/D65887

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/AArch64/vecreduce-and-legalization.ll
  test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
  test/CodeGen/WebAssembly/simd-arith.ll
  test/CodeGen/WebAssembly/simd-extended-extract.ll
  test/CodeGen/X86/bitcast-vector-bool.ll
  test/CodeGen/X86/promote-vec3.ll
  test/CodeGen/X86/vec_smulo.ll
  test/CodeGen/X86/vec_umulo.ll
  test/CodeGen/X86/vector-reduce-mul-widen.ll
  test/CodeGen/X86/vector-reduce-mul.ll
  test/CodeGen/X86/xor.ll

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