[llvm] r368167 - [RISCV][NFC] Document RISC-V-specific assembly constraints

[Sam Elliott via llvm-commits]

Author: lenary
Date: Wed Aug  7 06:08:07 2019
New Revision: 368167

URL: http://llvm.org/viewvc/llvm-project?rev=368167&view=rev
Log:
[RISCV][NFC] Document RISC-V-specific assembly constraints

Modified:
    llvm/trunk/docs/LangRef.rst

Modified: llvm/trunk/docs/LangRef.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=368167&r1=368166&r2=368167&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.rst (original)
+++ llvm/trunk/docs/LangRef.rst Wed Aug  7 06:08:07 2019
@@ -3952,6 +3952,17 @@ PowerPC:
 - ``ws``: A 32 or 64-bit floating-point register, from the full VSX register
   set.
 
+RISC-V:
+
+- ``A``: An address operand (using a general-purpose register, without an
+  offset).
+- ``I``: A 12-bit signed integer immediate operand.
+- ``J``: A zero integer immediate operand.
+- ``K``: A 5-bit unsigned integer immediate operand.
+- ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
+- ``r``: A 32- or 64-bit general-purpose register (depending on the platform
+  ``XLEN``).
+
 Sparc:
 
 - ``I``: An immediate 13-bit signed integer.