[llvm] r367972 - gn build: Add AMDGPU target
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 5 19:25:49 PDT 2019
Author: nico
Date: Mon Aug 5 19:25:49 2019
New Revision: 367972
URL: http://llvm.org/viewvc/llvm-project?rev=367972&view=rev
Log:
gn build: Add AMDGPU target
Differential Revision: https://reviews.llvm.org/D65767
Added:
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/
llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn
Modified:
llvm/trunk/utils/gn/TODO.txt
llvm/trunk/utils/gn/secondary/llvm/lib/Target/targets.gni
Modified: llvm/trunk/utils/gn/TODO.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/TODO.txt?rev=367972&r1=367971&r2=367972&view=diff
==============================================================================
--- llvm/trunk/utils/gn/TODO.txt (original)
+++ llvm/trunk/utils/gn/TODO.txt Mon Aug 5 19:25:49 2019
@@ -4,7 +4,7 @@ Ideas for things to do:
- once there are more projects, have an llvm_enable_projects arg, modeled
after llvm_targets_to_build in the GN build
- a check-all build target that runs test of all projects
-- more targets (AMDGPU ARC AVR MSP430 XCore)
+- more targets (ARC AVR MSP430 XCore)
- example: https://reviews.llvm.org/D56416
- investigate feasibility of working `gn check`
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/AsmParser/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,24 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("AMDGPUGenAsmMatcher") {
+ visibility = [ ":AsmParser" ]
+ args = [ "-gen-asm-matcher" ]
+ td_file = "../AMDGPU.td"
+}
+
+static_library("AsmParser") {
+ output_name = "LLVMAMDGPUAsmParser"
+ deps = [
+ ":AMDGPUGenAsmMatcher",
+ "//llvm/lib/MC",
+ "//llvm/lib/MC/MCParser",
+ "//llvm/lib/Support",
+ "//llvm/lib/Target/AMDGPU/MCTargetDesc",
+ "//llvm/lib/Target/AMDGPU/TargetInfo",
+ "//llvm/lib/Target/AMDGPU/Utils",
+ ]
+ include_dirs = [ ".." ]
+ sources = [
+ "AMDGPUAsmParser.cpp",
+ ]
+}
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,197 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("AMDGPUGenAsmMatcher") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-asm-matcher" ]
+ td_file = "AMDGPU.td"
+}
+
+tablegen("AMDGPUGenCallingConv") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-callingconv" ]
+ td_file = "AMDGPU.td"
+}
+
+tablegen("AMDGPUGenDAGISel") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-dag-isel" ]
+ td_file = "AMDGPU.td"
+}
+
+tablegen("AMDGPUGenGlobalISel") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-global-isel" ]
+ td_file = "AMDGPUGISel.td"
+}
+
+tablegen("AMDGPUGenMCPseudoLowering") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-pseudo-lowering" ]
+ td_file = "AMDGPU.td"
+}
+
+tablegen("AMDGPUGenRegisterBank") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-register-bank" ]
+ td_file = "AMDGPU.td"
+}
+
+tablegen("R600GenCallingConv") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-callingconv" ]
+ td_file = "R600.td"
+}
+
+tablegen("R600GenDAGISel") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-dag-isel" ]
+ td_file = "R600.td"
+}
+
+tablegen("R600GenDFAPacketizer") {
+ visibility = [ ":LLVMAMDGPUCodeGen" ]
+ args = [ "-gen-dfa-packetizer" ]
+ td_file = "R600.td"
+}
+
+static_library("LLVMAMDGPUCodeGen") {
+ deps = [
+ ":AMDGPUGenAsmMatcher",
+ ":AMDGPUGenCallingConv",
+ ":AMDGPUGenDAGISel",
+ ":AMDGPUGenGlobalISel",
+ ":AMDGPUGenMCPseudoLowering",
+ ":AMDGPUGenRegisterBank",
+ ":R600GenCallingConv",
+ ":R600GenDAGISel",
+ ":R600GenDFAPacketizer",
+ "MCTargetDesc",
+ "TargetInfo",
+ "Utils",
+ "//llvm/lib/Analysis",
+ "//llvm/lib/CodeGen",
+ "//llvm/lib/CodeGen/AsmPrinter",
+ "//llvm/lib/CodeGen/GlobalISel",
+ "//llvm/lib/CodeGen/MIRParser",
+ "//llvm/lib/CodeGen/SelectionDAG",
+ "//llvm/lib/IR",
+ "//llvm/lib/MC",
+ "//llvm/lib/Support",
+ "//llvm/lib/Target",
+ "//llvm/lib/Transforms/IPO",
+ "//llvm/lib/Transforms/Scalar",
+ "//llvm/lib/Transforms/Utils",
+ ]
+ include_dirs = [ "." ]
+ sources = [
+ "AMDGPUAliasAnalysis.cpp",
+ "AMDGPUAlwaysInlinePass.cpp",
+ "AMDGPUAnnotateKernelFeatures.cpp",
+ "AMDGPUAnnotateUniformValues.cpp",
+ "AMDGPUArgumentUsageInfo.cpp",
+ "AMDGPUAsmPrinter.cpp",
+ "AMDGPUAtomicOptimizer.cpp",
+ "AMDGPUCallLowering.cpp",
+ "AMDGPUCodeGenPrepare.cpp",
+ "AMDGPUFixFunctionBitcasts.cpp",
+ "AMDGPUFrameLowering.cpp",
+ "AMDGPUHSAMetadataStreamer.cpp",
+ "AMDGPUISelDAGToDAG.cpp",
+ "AMDGPUISelLowering.cpp",
+ "AMDGPUInline.cpp",
+ "AMDGPUInstrInfo.cpp",
+ "AMDGPUInstructionSelector.cpp",
+ "AMDGPULegalizerInfo.cpp",
+ "AMDGPULibCalls.cpp",
+ "AMDGPULibFunc.cpp",
+ "AMDGPULowerIntrinsics.cpp",
+ "AMDGPULowerKernelArguments.cpp",
+ "AMDGPULowerKernelAttributes.cpp",
+ "AMDGPUMCInstLower.cpp",
+ "AMDGPUMachineCFGStructurizer.cpp",
+ "AMDGPUMachineFunction.cpp",
+ "AMDGPUMachineModuleInfo.cpp",
+ "AMDGPUMacroFusion.cpp",
+ "AMDGPUOpenCLEnqueuedBlockLowering.cpp",
+ "AMDGPUPerfHintAnalysis.cpp",
+ "AMDGPUPromoteAlloca.cpp",
+ "AMDGPUPropagateAttributes.cpp",
+ "AMDGPURegisterBankInfo.cpp",
+ "AMDGPURegisterInfo.cpp",
+ "AMDGPURewriteOutArguments.cpp",
+ "AMDGPUSubtarget.cpp",
+ "AMDGPUTargetMachine.cpp",
+ "AMDGPUTargetObjectFile.cpp",
+ "AMDGPUTargetTransformInfo.cpp",
+ "AMDGPUUnifyDivergentExitNodes.cpp",
+ "AMDGPUUnifyMetadata.cpp",
+ "AMDILCFGStructurizer.cpp",
+ "GCNDPPCombine.cpp",
+ "GCNHazardRecognizer.cpp",
+ "GCNILPSched.cpp",
+ "GCNIterativeScheduler.cpp",
+ "GCNMinRegStrategy.cpp",
+ "GCNNSAReassign.cpp",
+ "GCNRegBankReassign.cpp",
+ "GCNRegPressure.cpp",
+ "GCNSchedStrategy.cpp",
+ "R600AsmPrinter.cpp",
+ "R600ClauseMergePass.cpp",
+ "R600ControlFlowFinalizer.cpp",
+ "R600EmitClauseMarkers.cpp",
+ "R600ExpandSpecialInstrs.cpp",
+ "R600FrameLowering.cpp",
+ "R600ISelLowering.cpp",
+ "R600InstrInfo.cpp",
+ "R600MachineFunctionInfo.cpp",
+ "R600MachineScheduler.cpp",
+ "R600OpenCLImageTypeLoweringPass.cpp",
+ "R600OptimizeVectorRegisters.cpp",
+ "R600Packetizer.cpp",
+ "R600RegisterInfo.cpp",
+ "SIAddIMGInit.cpp",
+ "SIAnnotateControlFlow.cpp",
+ "SIFixSGPRCopies.cpp",
+ "SIFixVGPRCopies.cpp",
+ "SIFixupVectorISel.cpp",
+ "SIFoldOperands.cpp",
+ "SIFormMemoryClauses.cpp",
+ "SIFrameLowering.cpp",
+ "SIISelLowering.cpp",
+ "SIInsertSkips.cpp",
+ "SIInsertWaitcnts.cpp",
+ "SIInstrInfo.cpp",
+ "SILoadStoreOptimizer.cpp",
+ "SILowerControlFlow.cpp",
+ "SILowerI1Copies.cpp",
+ "SILowerSGPRSpills.cpp",
+ "SIMachineFunctionInfo.cpp",
+ "SIMachineScheduler.cpp",
+ "SIMemoryLegalizer.cpp",
+ "SIModeRegister.cpp",
+ "SIOptimizeExecMasking.cpp",
+ "SIOptimizeExecMaskingPreRA.cpp",
+ "SIPeepholeSDWA.cpp",
+ "SIPreAllocateWWMRegs.cpp",
+ "SIRegisterInfo.cpp",
+ "SIShrinkInstructions.cpp",
+ "SIWholeQuadMode.cpp",
+ ]
+}
+
+# This is a bit different from most build files: Due to this group
+# having the directory's name, "//llvm/lib/Target/AMDGPU" will refer to this
+# target, which pulls in the code in this directory *and all subdirectories*.
+# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
+# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
+# different behavior.
+group("AMDGPU") {
+ deps = [
+ ":LLVMAMDGPUCodeGen",
+ "AsmParser",
+ "Disassembler",
+ "MCTargetDesc",
+ "TargetInfo",
+ "Utils",
+ ]
+}
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,24 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("AMDGPUGenDisassemblerTables") {
+ visibility = [ ":Disassembler" ]
+ args = [ "-gen-disassembler" ]
+ td_file = "../AMDGPU.td"
+}
+
+static_library("Disassembler") {
+ output_name = "LLVMAMDGPUDisassembler"
+ deps = [
+ ":AMDGPUGenDisassemblerTables",
+ "//llvm/lib/MC",
+ "//llvm/lib/MC/MCDisassembler",
+ "//llvm/lib/Support",
+ "//llvm/lib/Target/AMDGPU/MCTargetDesc",
+ "//llvm/lib/Target/AMDGPU/TargetInfo",
+ "//llvm/lib/Target/AMDGPU/Utils",
+ ]
+ include_dirs = [ ".." ]
+ sources = [
+ "AMDGPUDisassembler.cpp",
+ ]
+}
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,112 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("AMDGPUGenAsmWriter") {
+ visibility = [ ":MCTargetDesc" ]
+ args = [ "-gen-asm-writer" ]
+ td_file = "../AMDGPU.td"
+}
+
+tablegen("AMDGPUGenInstrInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-instr-info" ]
+ td_file = "../AMDGPU.td"
+}
+
+tablegen("AMDGPUGenMCCodeEmitter") {
+ visibility = [ ":MCTargetDesc" ]
+ args = [ "-gen-emitter" ]
+ td_file = "../AMDGPU.td"
+}
+
+tablegen("AMDGPUGenRegisterInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-register-info" ]
+ td_file = "../AMDGPU.td"
+}
+
+tablegen("AMDGPUGenSubtargetInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-subtarget" ]
+ td_file = "../AMDGPU.td"
+}
+
+tablegen("R600GenAsmWriter") {
+ visibility = [ ":MCTargetDesc" ]
+ args = [ "-gen-asm-writer" ]
+ td_file = "../R600.td"
+}
+
+tablegen("R600GenInstrInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-instr-info" ]
+ td_file = "../R600.td"
+}
+
+tablegen("R600GenMCCodeEmitter") {
+ visibility = [ ":MCTargetDesc" ]
+ args = [ "-gen-emitter" ]
+ td_file = "../R600.td"
+}
+
+tablegen("R600GenRegisterInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-register-info" ]
+ td_file = "../R600.td"
+}
+
+tablegen("R600GenSubtargetInfo") {
+ visibility = [ ":tablegen" ]
+ args = [ "-gen-subtarget" ]
+ td_file = "../R600.td"
+}
+
+# This should contain tablegen targets generating .inc files included
+# by other targets. .inc files only used by .cpp files in this directory
+# should be in deps on the static_library instead.
+group("tablegen") {
+ visibility = [
+ ":MCTargetDesc",
+ "../Utils",
+ ]
+ public_deps = [
+ ":AMDGPUGenInstrInfo",
+ ":AMDGPUGenRegisterInfo",
+ ":AMDGPUGenSubtargetInfo",
+ ":R600GenInstrInfo",
+ ":R600GenRegisterInfo",
+ ":R600GenSubtargetInfo",
+ ]
+}
+
+static_library("MCTargetDesc") {
+ output_name = "LLVMAMDGPUDesc"
+ public_deps = [
+ ":tablegen",
+ ]
+ deps = [
+ ":AMDGPUGenAsmWriter",
+ ":AMDGPUGenMCCodeEmitter",
+ ":R600GenAsmWriter",
+ ":R600GenMCCodeEmitter",
+ "//llvm/lib/BinaryFormat",
+ "//llvm/lib/IR",
+ "//llvm/lib/MC",
+ "//llvm/lib/Support",
+ "//llvm/lib/Target/AMDGPU/TargetInfo",
+ "//llvm/lib/Target/AMDGPU/Utils",
+ ]
+ include_dirs = [ ".." ]
+ sources = [
+ "AMDGPUAsmBackend.cpp",
+ "AMDGPUELFObjectWriter.cpp",
+ "AMDGPUELFStreamer.cpp",
+ "AMDGPUInstPrinter.cpp",
+ "AMDGPUMCAsmInfo.cpp",
+ "AMDGPUMCCodeEmitter.cpp",
+ "AMDGPUMCTargetDesc.cpp",
+ "AMDGPUTargetStreamer.cpp",
+ "R600MCCodeEmitter.cpp",
+ "R600MCTargetDesc.cpp",
+ "SIMCCodeEmitter.cpp",
+ ]
+}
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/TargetInfo/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,10 @@
+static_library("TargetInfo") {
+ output_name = "LLVMAMDGPUInfo"
+ deps = [
+ "//llvm/lib/Support",
+ ]
+ include_dirs = [ ".." ]
+ sources = [
+ "AMDGPUTargetInfo.cpp",
+ ]
+}
Added: llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn?rev=367972&view=auto
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn (added)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/AMDGPU/Utils/BUILD.gn Mon Aug 5 19:25:49 2019
@@ -0,0 +1,33 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("AMDGPUGenSearchableTables") {
+ visibility = [ ":Utils" ]
+ args = [ "-gen-searchable-tables" ]
+ td_file = "../AMDGPU.td"
+}
+
+static_library("Utils") {
+ output_name = "LLVMAMDGPUUtils"
+ public_deps = [
+ ":AMDGPUGenSearchableTables",
+ ]
+ deps = [
+ "//llvm/lib/BinaryFormat",
+ "//llvm/lib/IR",
+ "//llvm/lib/MC",
+ "//llvm/lib/Support",
+
+ # MCTargetDesc depends on Utils, so we can't depend on the full
+ # MCTargetDesc target here: it would form a cycle.
+ "//llvm/lib/Target/AMDGPU/MCTargetDesc:tablegen",
+ ]
+
+ # AMDGPUBaseInfo.h includes a header from MCTargetDesc :-/
+ include_dirs = [ ".." ]
+ sources = [
+ "AMDGPUAsmUtils.cpp",
+ "AMDGPUBaseInfo.cpp",
+ "AMDGPUPALMetadata.cpp",
+ "AMDKernelCodeTUtils.cpp",
+ ]
+}
Modified: llvm/trunk/utils/gn/secondary/llvm/lib/Target/targets.gni
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/gn/secondary/llvm/lib/Target/targets.gni?rev=367972&r1=367971&r2=367972&view=diff
==============================================================================
--- llvm/trunk/utils/gn/secondary/llvm/lib/Target/targets.gni (original)
+++ llvm/trunk/utils/gn/secondary/llvm/lib/Target/targets.gni Mon Aug 5 19:25:49 2019
@@ -21,6 +21,7 @@ if (llvm_targets_to_build == "host") {
# FIXME: Port the remaining targets.
llvm_targets_to_build = [
"AArch64",
+ "AMDGPU",
"ARM",
"BPF",
"Hexagon",
@@ -46,6 +47,8 @@ llvm_build_X86 = false
foreach(target, llvm_targets_to_build) {
if (target == "AArch64") {
llvm_build_AArch64 = true
+ } else if (target == "AMDGPU") {
+ # Nothing to do.
} else if (target == "ARM") {
llvm_build_ARM = true
} else if (target == "BPF") {
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