[PATCH] D65741: [X86][SSE] Lower shuffle as ANY_EXTEND_VECTOR_INREG

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, andreadb.
Herald added a project: LLVM.

On SSE41+ targets we always lower vector shuffles to ZERO_EXTEND_VECTOR_INREG, even if we don't need the extended bits.

This patch relaxes this so that we lower to ANY_EXTEND_VECTOR_INREG if we can, meaning that shuffle combines have a better idea of what elements need to be kept zero. This helps the multiple reduction code as we can now combine away a lot more of the pack+extend codes.

This exposes an issue in some PMULLD -> PMADDWD combine tests which were relying on the ZERO_EXTEND_VECTOR_INREG to know we had upper bits set to zero, I've put in a hack to avoid this but can revisit this if we need a more powerful solution.

Otherwise, in most cases this has only a small effect - notably if the shuffle combine to PSHUFB where we can now see the undef elements.


Repository:
  rL LLVM

https://reviews.llvm.org/D65741

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/load-partial.ll
  test/CodeGen/X86/oddsubvector.ll
  test/CodeGen/X86/pr35918.ll
  test/CodeGen/X86/vector-narrow-binop.ll
  test/CodeGen/X86/vector-reduce-mul-widen.ll
  test/CodeGen/X86/vector-reduce-mul.ll
  test/CodeGen/X86/vector-shuffle-256-v8.ll
  test/CodeGen/X86/vector-shuffle-combining.ll

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