[PATCH] D47927: [WIP][TargetLowering] Simplify expansion of S{ADD,SUB}O

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 updated this revision to Diff 213056.
rogfer01 retitled this revision from "[RISCV] Custom lower ISD::{U,S}{ADD,SUB}O nodes" to "[WIP][TargetLowering] Simplify expansion of S{ADD,SUB}O".
rogfer01 edited the summary of this revision.
rogfer01 added a reviewer: efriedma.
rogfer01 set the repository for this revision to rG LLVM Github Monorepo.
rogfer01 added a comment.
Herald added subscribers: jrtc27, hiraditya, javed.absar.
Herald added a project: LLVM.

ChangeLog:

- Remove RISC-V dependent expansions
- Simplify current target-independent expansion of `S{ADD,SUB}O`. Not considering `U{ADD,SUB}O` anymore.
- Update tests that saw codegen changes after this

For now marking this as WIP because I want to test this some more.

Also test `CodeGen/AMDGPU/saddo.ll` needs updating but I'm rather clueless when it comes to that target.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D47927/new/

https://reviews.llvm.org/D47927

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/ARM/addsubo-legalization.ll
  llvm/test/CodeGen/RISCV/arith-with-overflow.ll
  llvm/test/CodeGen/X86/combine-mulo.ll
  llvm/test/CodeGen/X86/mulo-pow2.ll
  llvm/test/CodeGen/X86/sadd_sat.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/ssub_sat.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll
  llvm/test/CodeGen/X86/vec_saddo.ll
  llvm/test/CodeGen/X86/vec_ssubo.ll

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