[PATCH] D65683: MVT: Add v3i16/v3f16 vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D65683#1613936 <https://reviews.llvm.org/D65683#1613936>, @craig.topper wrote:

> In D65683#1613922 <https://reviews.llvm.org/D65683#1613922>, @arsenm wrote:
>
> > In D65683#1613355 <https://reviews.llvm.org/D65683#1613355>, @craig.topper wrote:
> >
> > > I think there's a bug in computeRegisterProperties for TypeWidenVector. For non-power2 vectors we need to go the next largest power of 2 vector. Currently its goes through the loop looking for a legal vector with more elements. For X86 it takes v3i16 all the way to v8i16. It should only take it to v4i16.
> >
> >
> > Why should it go to v4i16? I don't see that added as a legal type in x86? I only see v8i16, v16i16, and v32i16 as possible legal vectors
>
>
> I’m only saying that because that’s what EVT did. It doesn’t seem like a good design to change behavior of other targets when one target needs a new MVT.


The MVT vs. EVT distinction is a broken design, which thankfully GlobalISel fixes. The question going forward is whether maintaining compatibility with the traditionally broken non-power-of-2 support is something worth maintaining


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