[PATCH] D65607: [DAGCombiner] try to convert opposing shifts to casts

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D65607#1613432 <https://reviews.llvm.org/D65607#1613432>, @mstorsjo wrote:

> In D65607#1613403 <https://reviews.llvm.org/D65607#1613403>, @lebedev.ri wrote:
>
> > In D65607#1613401 <https://reviews.llvm.org/D65607#1613401>, @mstorsjo wrote:
> >
> > > This caused failed asserts ("Unexpected illegal type!" in LegalizeDAG) when building Qt,  with https://martin.st/temp/qpainterpath-preproc.cpp, built with `clang++ -target i686-w64-mingw32 -c -O3 -std=c++17 qpainterpath-preproc.cpp`. Will file a full proper bug later if necessary.
> >
> >
> > Would be good to have a reproducer, even just `N->dumprFull()` may shed some light.
>
>
> `Node->dumprFull();` for the failed assert prints
>
>   t51: i32 = sign_extend t50
>     t50: i29 = add t48, Constant:i29<-3>
>       t48: i29 = truncate t46
>         t46: i32 = <<Unknown Node #438>> t8, Constant:i32<3>
>           t8: i32,ch = CopyFromReg t0, Register:i32 %13
>             t7: i32 = Register %13
>           t45: i32 = Constant<3>
>       t49: i29 = Constant<-3>
>


I can guess how we should limit this transform, but my translation of that DAG to IR does not crash for me:

  define i32 @trunc29(i32 %x) nounwind {
    %u2 = trunc i32 %x to i29
    %u3 = add i29 %u2, -3
    %r = sext i29 %u3 to i32
    ret i32 %r
  }

...so I need more info.


Repository:
  rL LLVM

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