[llvm] r367732 - [PowerPC][NFC][MachinePipeliner] Add some regression testcases
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 2 18:13:04 PDT 2019
Hi Jinsong,
I've reverted this temporarily in r367741 since it was breaking some
bots, for example:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/13893/steps/check-llvm%20msan/logs/stdio
let me know if there's anything you need.
Thanks!
-eric
On Fri, Aug 2, 2019 at 3:26 PM Jinsong Ji via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: jsji
> Date: Fri Aug 2 15:27:44 2019
> New Revision: 367732
>
> URL: http://llvm.org/viewvc/llvm-project?rev=367732&view=rev
> Log:
> [PowerPC][NFC][MachinePipeliner] Add some regression testcases
>
> Exposed by refactoring in https://reviews.llvm.org/D64665.
>
> Added:
> llvm/trunk/test/CodeGen/PowerPC/sms-cpy-1.ll
> llvm/trunk/test/CodeGen/PowerPC/sms-phi-1.ll
> llvm/trunk/test/CodeGen/PowerPC/sms-phi-2.ll
> llvm/trunk/test/CodeGen/PowerPC/sms-phi-3.ll
> llvm/trunk/test/CodeGen/PowerPC/sms-phi-5.ll
>
> Added: llvm/trunk/test/CodeGen/PowerPC/sms-cpy-1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sms-cpy-1.ll?rev=367732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/sms-cpy-1.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/sms-cpy-1.ll Fri Aug 2 15:27:44 2019
> @@ -0,0 +1,105 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
> +; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
> +
> + at .str.28 = external unnamed_addr constant [69 x i8], align 1
> +
> +define void @print_res() unnamed_addr {
> +; CHECK-LABEL: print_res:
> +; CHECK: # %bb.0:
> +; CHECK-NEXT: mflr 0
> +; CHECK-NEXT: std 0, 16(1)
> +; CHECK-NEXT: stdu 1, -128(1)
> +; CHECK-NEXT: .cfi_def_cfa_offset 128
> +; CHECK-NEXT: .cfi_offset lr, 16
> +; CHECK-NEXT: lwz 3, 0(3)
> +; CHECK-NEXT: addi 3, 3, -1
> +; CHECK-NEXT: clrldi 4, 3, 32
> +; CHECK-NEXT: cmplwi 0, 3, 1
> +; CHECK-NEXT: li 3, 1
> +; CHECK-NEXT: isel 3, 4, 3, 1
> +; CHECK-NEXT: li 4, 2
> +; CHECK-NEXT: addi 3, 3, -1
> +; CHECK-NEXT: cmpldi 3, 2
> +; CHECK-NEXT: isel 3, 3, 4, 0
> +; CHECK-NEXT: li 4, 0
> +; CHECK-NEXT: addi 3, 3, 1
> +; CHECK-NEXT: li 5, 0
> +; CHECK-NEXT: li 7, -1
> +; CHECK-NEXT: mtctr 3
> +; CHECK-NEXT: lbz 5, 0(5)
> +; CHECK-NEXT: li 3, 1
> +; CHECK-NEXT: bdz .LBB0_4
> +; CHECK-NEXT: # %bb.1:
> +; CHECK-NEXT: xori 5, 5, 84
> +; CHECK-NEXT: cntlzw 5, 5
> +; CHECK-NEXT: srwi 6, 5, 5
> +; CHECK-NEXT: clrldi 5, 7, 32
> +; CHECK-NEXT: addi 7, 7, -1
> +; CHECK-NEXT: lbz 5, 0(5)
> +; CHECK-NEXT: addi 3, 3, 1
> +; CHECK-NEXT: bdz .LBB0_3
> +; CHECK-NEXT: .p2align 4
> +; CHECK-NEXT: .LBB0_2: #
> +; CHECK-NEXT: xori 5, 5, 84
> +; CHECK-NEXT: clrldi 8, 7, 32
> +; CHECK-NEXT: add 4, 4, 6
> +; CHECK-NEXT: cntlzw 6, 5
> +; CHECK-NEXT: lbz 5, 0(8)
> +; CHECK-NEXT: addi 7, 7, -1
> +; CHECK-NEXT: addi 3, 3, 1
> +; CHECK-NEXT: srwi 6, 6, 5
> +; CHECK-NEXT: bdnz .LBB0_2
> +; CHECK-NEXT: .LBB0_3:
> +; CHECK-NEXT: add 4, 4, 6
> +; CHECK-NEXT: .LBB0_4:
> +; CHECK-NEXT: xori 5, 5, 84
> +; CHECK-NEXT: cntlzw 5, 5
> +; CHECK-NEXT: clrldi 3, 3, 32
> +; CHECK-NEXT: std 3, 104(1)
> +; CHECK-NEXT: addis 3, 2, .LC0 at toc@ha
> +; CHECK-NEXT: ld 3, .LC0 at toc@l(3)
> +; CHECK-NEXT: li 7, 0
> +; CHECK-NEXT: li 8, 3
> +; CHECK-NEXT: srwi 5, 5, 5
> +; CHECK-NEXT: add 4, 4, 5
> +; CHECK-NEXT: li 5, 0
> +; CHECK-NEXT: std 5, 120(1)
> +; CHECK-NEXT: li 5, 3
> +; CHECK-NEXT: std 5, 96(1)
> +; CHECK-NEXT: clrldi 6, 4, 32
> +; CHECK-NEXT: li 4, 3
> +; CHECK-NEXT: li 5, 0
> +; CHECK-NEXT: li 10, 0
> +; CHECK-NEXT: bl printf
> +; CHECK-NEXT: nop
> + %1 = load i32, i32* undef, align 4
> + %2 = add i32 %1, -1
> + %3 = zext i32 %2 to i64
> + %4 = zext i32 3 to i64
> + br label %5
> +
> +5: ; preds = %5, %0
> + %6 = phi i64 [ %16, %5 ], [ 0, %0 ]
> + %7 = phi i32 [ %15, %5 ], [ 0, %0 ]
> + %8 = trunc i64 %6 to i32
> + %9 = sub i32 0, %8
> + %10 = zext i32 %9 to i64
> + %11 = getelementptr inbounds i8, i8* null, i64 %10
> + %12 = load i8, i8* %11, align 1
> + %13 = icmp eq i8 %12, 84
> + %14 = zext i1 %13 to i32
> + %15 = add i32 %7, %14
> + %16 = add nuw nsw i64 %6, 1
> + %17 = icmp ult i64 %16, %3
> + %18 = icmp ult i64 %16, %4
> + %19 = and i1 %18, %17
> + br i1 %19, label %5, label %20
> +
> +20: ; preds = %5
> + %21 = trunc i64 %16 to i32
> + call void (i8*, ...) @printf(i8* getelementptr inbounds ([69 x i8], [69 x i8]* @.str.28, i64 0, i64 0), i32 zeroext 3, i32 zeroext undef, i32 zeroext %15, i32 zeroext undef, i32 zeroext 3, i8* undef, i32 zeroext undef, i32 zeroext 3, i32 zeroext %21, i8* undef, i32 zeroext undef) #1
> + unreachable
> +}
> +
> +declare void @printf(i8*, ...) local_unnamed_addr #0
>
> Added: llvm/trunk/test/CodeGen/PowerPC/sms-phi-1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sms-phi-1.ll?rev=367732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/sms-phi-1.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/sms-phi-1.ll Fri Aug 2 15:27:44 2019
> @@ -0,0 +1,67 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
> +; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
> +
> +define void @main() local_unnamed_addr #0 {
> +; CHECK-LABEL: main:
> +; CHECK: # %bb.0:
> +; CHECK-NEXT: mflr 0
> +; CHECK-NEXT: .cfi_def_cfa_offset 48
> +; CHECK-NEXT: .cfi_offset lr, 16
> +; CHECK-NEXT: .cfi_offset r30, -16
> +; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
> +; CHECK-NEXT: std 0, 16(1)
> +; CHECK-NEXT: stdu 1, -48(1)
> +; CHECK-NEXT: bl strtol
> +; CHECK-NEXT: nop
> +; CHECK-NEXT: mr 30, 3
> +; CHECK-NEXT: bl calloc
> +; CHECK-NEXT: nop
> +; CHECK-NEXT: clrldi 4, 30, 32
> +; CHECK-NEXT: li 5, 0
> +; CHECK-NEXT: addi 3, 3, -4
> +; CHECK-NEXT: mtctr 4
> +; CHECK-NEXT: mullw 4, 5, 5
> +; CHECK-NEXT: li 6, 1
> +; CHECK-NEXT: bdz .LBB0_3
> +; CHECK-NEXT: # %bb.1:
> +; CHECK-NEXT: stwu 4, 4(3)
> +; CHECK-NEXT: mullw 4, 6, 6
> +; CHECK-NEXT: addi 5, 6, 1
> +; CHECK-NEXT: bdz .LBB0_3
> +; CHECK-NEXT: .p2align 4
> +; CHECK-NEXT: .LBB0_2: #
> +; CHECK-NEXT: stwu 4, 4(3)
> +; CHECK-NEXT: mullw 4, 5, 5
> +; CHECK-NEXT: addi 5, 5, 1
> +; CHECK-NEXT: bdnz .LBB0_2
> +; CHECK-NEXT: .LBB0_3:
> +; CHECK-NEXT: stwu 4, 4(3)
> +; CHECK-NEXT: addi 1, 1, 48
> +; CHECK-NEXT: ld 0, 16(1)
> +; CHECK-NEXT: mtlr 0
> +; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
> +; CHECK-NEXT: blr
> + %1 = tail call i64 @strtol()
> + %2 = trunc i64 %1 to i32
> + %3 = tail call noalias i8* @calloc()
> + %4 = bitcast i8* %3 to i32*
> + %5 = zext i32 %2 to i64
> + br label %6
> +
> +6: ; preds = %6, %0
> + %7 = phi i64 [ %11, %6 ], [ 0, %0 ]
> + %8 = trunc i64 %7 to i32
> + %9 = mul nsw i32 %8, %8
> + %10 = getelementptr inbounds i32, i32* %4, i64 %7
> + store i32 %9, i32* %10, align 4
> + %11 = add nuw nsw i64 %7, 1
> + %12 = icmp eq i64 %11, %5
> + br i1 %12, label %13, label %6
> +
> +13: ; preds = %6
> + ret void
> +}
> +
> +declare i8* @calloc() local_unnamed_addr
> +declare i64 @strtol() local_unnamed_addr
>
> Added: llvm/trunk/test/CodeGen/PowerPC/sms-phi-2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sms-phi-2.ll?rev=367732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/sms-phi-2.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/sms-phi-2.ll Fri Aug 2 15:27:44 2019
> @@ -0,0 +1,69 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
> +; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
> +
> +define void @phi2(i32, i32, i8*) local_unnamed_addr {
> +; CHECK-LABEL: phi2:
> +; CHECK: # %bb.0:
> +; CHECK-NEXT: divw 8, 3, 4
> +; CHECK-NEXT: li 5, 55
> +; CHECK-NEXT: li 6, 48
> +; CHECK-NEXT: mtctr 3
> +; CHECK-NEXT: bdz .LBB0_4
> +; CHECK-NEXT: # %bb.1:
> +; CHECK-NEXT: divw 9, 8, 4
> +; CHECK-NEXT: mullw 7, 8, 4
> +; CHECK-NEXT: subf 3, 7, 3
> +; CHECK-NEXT: cmplwi 3, 10
> +; CHECK-NEXT: isel 7, 6, 5, 0
> +; CHECK-NEXT: add 3, 7, 3
> +; CHECK-NEXT: stbu 3, -1(7)
> +; CHECK-NEXT: mr 3, 8
> +; CHECK-NEXT: bdz .LBB0_3
> +; CHECK-NEXT: .p2align 4
> +; CHECK-NEXT: .LBB0_2: #
> +; CHECK-NEXT: mr 3, 9
> +; CHECK-NEXT: mullw 9, 9, 4
> +; CHECK-NEXT: divw 10, 3, 4
> +; CHECK-NEXT: subf 8, 9, 8
> +; CHECK-NEXT: cmplwi 8, 10
> +; CHECK-NEXT: isel 9, 6, 5, 0
> +; CHECK-NEXT: add 8, 9, 8
> +; CHECK-NEXT: mr 9, 10
> +; CHECK-NEXT: stbu 8, -1(7)
> +; CHECK-NEXT: mr 8, 3
> +; CHECK-NEXT: bdnz .LBB0_2
> +; CHECK-NEXT: .LBB0_3:
> +; CHECK-NEXT: mr 8, 9
> +; CHECK-NEXT: b .LBB0_5
> +; CHECK-NEXT: .LBB0_4:
> +; CHECK-NEXT: # implicit-def: $x7
> +; CHECK-NEXT: .LBB0_5:
> +; CHECK-NEXT: mullw 4, 8, 4
> +; CHECK-NEXT: subf 3, 4, 3
> +; CHECK-NEXT: cmplwi 3, 10
> +; CHECK-NEXT: isel 4, 6, 5, 0
> +; CHECK-NEXT: add 3, 4, 3
> +; CHECK-NEXT: stbu 3, -1(7)
> +; CHECK-NEXT: blr
> + br label %4
> +
> +4: ; preds = %4, %3
> + %5 = phi i64 [ %7, %4 ], [ undef, %3 ]
> + %6 = phi i32 [ %8, %4 ], [ %0, %3 ]
> + %7 = add nsw i64 %5, -1
> + %8 = sdiv i32 %6, %1
> + %9 = mul nsw i32 %8, %1
> + %10 = sub nsw i32 %6, %9
> + %11 = icmp ult i32 %10, 10
> + %12 = trunc i32 %10 to i8
> + %13 = select i1 %11, i8 48, i8 55
> + %14 = add i8 %13, %12
> + %15 = getelementptr inbounds i8, i8* %2, i64 %7
> + store i8 %14, i8* %15, align 1
> + %16 = icmp sgt i64 %5, 1
> + br i1 %16, label %4, label %17
> +
> +17: ; preds = %4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/sms-phi-3.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sms-phi-3.ll?rev=367732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/sms-phi-3.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/sms-phi-3.ll Fri Aug 2 15:27:44 2019
> @@ -0,0 +1,89 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
> +; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
> +
> +%0 = type { double, double, double, i32, i32 }
> +declare i8* @malloc() local_unnamed_addr
> +
> +define void @phi3(i32*) local_unnamed_addr {
> +; CHECK-LABEL: phi3:
> +; CHECK: # %bb.0:
> +; CHECK-NEXT: mflr 0
> +; CHECK-NEXT: .cfi_def_cfa_offset 64
> +; CHECK-NEXT: .cfi_offset lr, 16
> +; CHECK-NEXT: .cfi_offset r29, -24
> +; CHECK-NEXT: .cfi_offset r30, -16
> +; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
> +; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
> +; CHECK-NEXT: std 0, 16(1)
> +; CHECK-NEXT: stdu 1, -64(1)
> +; CHECK-NEXT: mr 30, 3
> +; CHECK-NEXT: bl malloc
> +; CHECK-NEXT: nop
> +; CHECK-NEXT: mr 29, 3
> +; CHECK-NEXT: bl malloc
> +; CHECK-NEXT: nop
> +; CHECK-NEXT: addi 7, 30, -4
> +; CHECK-NEXT: mtctr 3
> +; CHECK-NEXT: lwzu 8, 4(7)
> +; CHECK-NEXT: addi 4, 29, -8
> +; CHECK-NEXT: li 5, 0
> +; CHECK-NEXT: bdz .LBB0_5
> +; CHECK-NEXT: # %bb.1:
> +; CHECK-NEXT: extswsli 6, 5, 5
> +; CHECK-NEXT: add 5, 8, 5
> +; CHECK-NEXT: lwzu 8, 4(7)
> +; CHECK-NEXT: bdz .LBB0_4
> +; CHECK-NEXT: # %bb.2:
> +; CHECK-NEXT: add 6, 3, 6
> +; CHECK-NEXT: stdu 6, 8(4)
> +; CHECK-NEXT: extswsli 6, 5, 5
> +; CHECK-NEXT: add 5, 8, 5
> +; CHECK-NEXT: lwzu 8, 4(7)
> +; CHECK-NEXT: bdz .LBB0_4
> +; CHECK-NEXT: .p2align 5
> +; CHECK-NEXT: .LBB0_3: #
> +; CHECK-NEXT: add 9, 3, 6
> +; CHECK-NEXT: extswsli 6, 5, 5
> +; CHECK-NEXT: add 5, 8, 5
> +; CHECK-NEXT: lwzu 8, 4(7)
> +; CHECK-NEXT: stdu 9, 8(4)
> +; CHECK-NEXT: bdnz .LBB0_3
> +; CHECK-NEXT: .LBB0_4:
> +; CHECK-NEXT: add 6, 3, 6
> +; CHECK-NEXT: stdu 6, 8(4)
> +; CHECK-NEXT: .LBB0_5:
> +; CHECK-NEXT: extswsli 5, 5, 5
> +; CHECK-NEXT: add 3, 3, 5
> +; CHECK-NEXT: stdu 3, 8(4)
> +; CHECK-NEXT: addi 1, 1, 64
> +; CHECK-NEXT: ld 0, 16(1)
> +; CHECK-NEXT: mtlr 0
> +; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
> +; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
> +; CHECK-NEXT: blr
> + %2 = tail call noalias i8* @malloc()
> + %3 = bitcast i8* %2 to %0**
> + %4 = tail call noalias i8* @malloc()
> + %5 = bitcast i8* %4 to %0*
> + br label %6
> +
> +6: ; preds = %6, %1
> + %7 = phi i64 [ %16, %6 ], [ 0, %1 ]
> + %8 = phi i32 [ %15, %6 ], [ 0, %1 ]
> + %9 = phi i64 [ %17, %6 ], [ undef, %1 ]
> + %10 = sext i32 %8 to i64
> + %11 = getelementptr inbounds %0, %0* %5, i64 %10
> + %12 = getelementptr inbounds %0*, %0** %3, i64 %7
> + store %0* %11, %0** %12, align 8
> + %13 = getelementptr inbounds i32, i32* %0, i64 %7
> + %14 = load i32, i32* %13, align 4
> + %15 = add nsw i32 %14, %8
> + %16 = add nuw nsw i64 %7, 1
> + %17 = add i64 %9, -1
> + %18 = icmp eq i64 %17, 0
> + br i1 %18, label %19, label %6
> +
> +19: ; preds = %6
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/sms-phi-5.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/sms-phi-5.ll?rev=367732&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/sms-phi-5.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/sms-phi-5.ll Fri Aug 2 15:27:44 2019
> @@ -0,0 +1,56 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
> +; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
> +
> +define void @phi5() unnamed_addr {
> +; CHECK-LABEL: phi5:
> +; CHECK: # %bb.0:
> +; CHECK-NEXT: # %bb.1:
> +; CHECK-NEXT: li 3, 0
> +; CHECK-NEXT: li 4, 1
> +; CHECK-NEXT: slw 3, 4, 3
> +; CHECK-NEXT: andi. 3, 3, 6336
> +; CHECK-NEXT: beqlr 0
> +; CHECK-NEXT: # %bb.2:
> +; CHECK-NEXT: lhz 3, 0(3)
> +; CHECK-NEXT: slwi 3, 3, 15
> +; CHECK-NEXT: clrlwi 3, 3, 31
> +; CHECK-NEXT: rlwinm 4, 3, 31, 17, 31
> +; CHECK-NEXT: or 3, 3, 4
> +; CHECK-NEXT: rlwimi 3, 3, 15, 0, 16
> +; CHECK-NEXT: # %bb.3:
> +; CHECK-NEXT: blr
> + switch i12 undef, label %21 [
> + i12 6, label %1
> + i12 7, label %1
> + i12 12, label %1
> + i12 11, label %1
> + ]
> +
> +1: ; preds = %0, %0, %0, %0
> + %2 = load i16, i16* undef, align 2
> + br label %3
> +
> +3: ; preds = %3, %1
> + %4 = phi i16 [ %18, %3 ], [ undef, %1 ]
> + %5 = phi i16 [ %13, %3 ], [ undef, %1 ]
> + %6 = phi i16 [ %11, %3 ], [ undef, %1 ]
> + %7 = phi i16 [ undef, %3 ], [ %2, %1 ]
> + %8 = phi i32 [ %19, %3 ], [ undef, %1 ]
> + %9 = lshr i16 %6, 1
> + %10 = shl i16 %7, 15
> + %11 = or i16 %10, %9
> + %12 = shl i16 %6, 15
> + %13 = or i16 %12, 0
> + %14 = and i16 %4, 1
> + %15 = lshr i16 %4, 1
> + %16 = shl i16 %5, 15
> + %17 = or i16 %14, %15
> + %18 = or i16 %17, %16
> + %19 = add i32 %8, -1
> + %20 = icmp eq i32 %19, 0
> + br i1 %20, label %21, label %3
> +
> +21: ; preds = %3, %0
> + ret void
> +}
>
>
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