[PATCH] D65653: [AArch64] Change location of frame-record within callee-save area.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: efriedma, rovka, rengolin, thegameg, greened, t.p.northover.
Herald added subscribers: arphaman, kristof.beyls, javed.absar, qcolombet.
sdesmalen added a child revision: D61437: [AArch64] Static (de)allocation of SVE stack objects..

This patch changes the location of the frame-record (FP, LR) to the 
bottom of the callee-saved area. According to the AAPCS the location of
the frame-record within the stackframe is unspecified (section 5.2.3 The 
Frame Pointer), so the compiler should be free to choose a different
location.

The reason for changing the location of the frame-record is to prepare
the frame for allocating an SVE area below the callee-saves. This way the 
compiler can use the VL-scaled addressing modes to directly access SVE 
objects from the frame-pointer.

            :                :   
        | stack |        | stack |
        |  args |        |  args |
        +-------+        +-------+
        |  x30  |        |  x19  |
        |  x29  |        |  x20  |
  FP -> |- - - -|        |  x21  |
        |  x19  |   ==>  |  x22  |
        |  x20  |        |- - - -|
        |  x21  |        |  x30  |
        |  x22  |        |  x29  |
        +-------+        +-------+ <- FP
        |///////|        |///////|         // realignment gap 
        |- - - -|        |- - - -|
        |spills/|        |spills/|
        | locals|        | locals|
  SP -> +-------+        +-------+ <- SP

Things to point out:

- The CFI instructions emit the FP/LR registers first (in the order as specified in the CallingConvention.td file) in order to support the Compact Unwinding format.

- The algorith to find a paired register should be prevented from accidentally pairing some callee-saved register with LR that is not FP, since they should always be paired together when the frame has a frame-record.


https://reviews.llvm.org/D65653

Files:
  lib/Target/AArch64/AArch64CallingConvention.td
  lib/Target/AArch64/AArch64FrameLowering.cpp
  test/CodeGen/AArch64/GlobalISel/swifterror.ll
  test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
  test/CodeGen/AArch64/aarch64-vector-pcs.mir
  test/CodeGen/AArch64/addsub-constant-folding.ll
  test/CodeGen/AArch64/alloca.ll
  test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll
  test/CodeGen/AArch64/arm64-anyregcc.ll
  test/CodeGen/AArch64/arm64-frame-index.ll
  test/CodeGen/AArch64/arm64-shrink-wrapping.ll
  test/CodeGen/AArch64/cgp-usubo.ll
  test/CodeGen/AArch64/fast-isel-sp-adjust.ll
  test/CodeGen/AArch64/irg_sp_tagp.ll
  test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
  test/CodeGen/AArch64/reverse-csr-restore-seq.mir
  test/CodeGen/AArch64/seh-finally.ll
  test/CodeGen/AArch64/shadow-call-stack.ll
  test/CodeGen/AArch64/sink-copy-for-shrink-wrap.ll
  test/CodeGen/AArch64/spill-stack-realignment.mir
  test/CodeGen/AArch64/sponentry.ll
  test/CodeGen/AArch64/stack-guard-reassign.ll
  test/CodeGen/AArch64/stack-guard-vaarg.ll
  test/CodeGen/AArch64/swifterror.ll
  test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll
  test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbits.ll
  test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
  test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-lowhigh.ll
  test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll
  test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
  test/CodeGen/AArch64/win64_vararg.ll
  test/CodeGen/AArch64/wineh-frame5.mir
  test/CodeGen/AArch64/wineh-frame7.mir
  test/CodeGen/AArch64/wineh-try-catch-realign.ll
  test/CodeGen/AArch64/wineh-try-catch.ll
  test/CodeGen/AArch64/wineh_shrinkwrap.mir

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