[llvm] r367670 - [IPRA][ARM] Disable no-CSR optimisation for ARM

[Oliver Stannard via llvm-commits]

Author: ostannard
Date: Fri Aug  2 03:23:17 2019
New Revision: 367670

URL: http://llvm.org/viewvc/llvm-project?rev=367670&view=rev
Log:
[IPRA][ARM] Disable no-CSR optimisation for ARM

This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.

Differential revision: https://reviews.llvm.org/D64910

Added:
    llvm/trunk/test/CodeGen/ARM/ipra-no-csr.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h
    llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
    llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.h

Modified: llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h?rev=367670&r1=367669&r2=367670&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetFrameLowering.h Fri Aug  2 03:23:17 2019
@@ -378,6 +378,11 @@ public:
     return true;
   }
 
+  /// Check if the no-CSR optimisation is profitable for the given function.
+  virtual bool isProfitableForNoCSROpt(const Function &F) const {
+    return true;
+  }
+
   /// Return initial CFA offset value i.e. the one valid at the beginning of the
   /// function (before any stack operations).
   virtual int getInitialCFAOffset(const MachineFunction &MF) const;

Modified: llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp?rev=367670&r1=367669&r2=367670&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp Fri Aug  2 03:23:17 2019
@@ -171,7 +171,8 @@ bool RegUsageInfoCollector::runOnMachine
       SetRegAsDefined(PReg);
   }
 
-  if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
+  if (TargetFrameLowering::isSafeForNoCSROpt(F) &&
+      MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
     ++NumCSROpt;
     LLVM_DEBUG(dbgs() << MF.getName()
                       << " function optimized for not having CSR.\n");

Modified: llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp?rev=367670&r1=367669&r2=367670&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetFrameLoweringImpl.cpp Fri Aug  2 03:23:17 2019
@@ -71,7 +71,9 @@ void TargetFrameLowering::determineCalle
 
   // When interprocedural register allocation is enabled caller saved registers
   // are preferred over callee saved registers.
-  if (MF.getTarget().Options.EnableIPRA && isSafeForNoCSROpt(MF.getFunction()))
+  if (MF.getTarget().Options.EnableIPRA &&
+      isSafeForNoCSROpt(MF.getFunction()) &&
+      isProfitableForNoCSROpt(MF.getFunction()))
     return;
 
   // Get the callee saved register list...

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.h?rev=367670&r1=367669&r2=367670&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.h Fri Aug  2 03:23:17 2019
@@ -63,6 +63,11 @@ public:
   bool enableShrinkWrapping(const MachineFunction &MF) const override {
     return true;
   }
+  bool isProfitableForNoCSROpt(const Function &F) const override {
+    // The no-CSR optimisation is bad for code size on ARM, because we can save
+    // many registers with a single PUSH/POP pair.
+    return false;
+  }
 
 private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,

Added: llvm/trunk/test/CodeGen/ARM/ipra-no-csr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ipra-no-csr.ll?rev=367670&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ipra-no-csr.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/ipra-no-csr.ll Fri Aug  2 03:23:17 2019
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple armv7a--none-eabi < %s              | FileCheck %s
+; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
+
+; Other targets disable callee-saved registers for internal functions when
+; using IPRA, but that isn't profitable for ARM because the PUSH/POP
+; instructions can more efficiently save registers than using individual
+; LDR/STRs in the caller.
+
+define internal void @callee() norecurse {
+; CHECK-LABEL: callee:
+entry:
+; CHECK: push {r4, lr}
+; CHECK: pop {r4, pc}
+  tail call void asm sideeffect "", "~{r4}"()
+  ret void
+}
+
+define void @caller() {
+entry:
+  call void @callee()
+  ret void
+}