[PATCH] D64910: [IPRA][ARM] Disable no-CSR optimisation for ARM

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard updated this revision to Diff 213003.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64910/new/

https://reviews.llvm.org/D64910

Files:
  llvm/include/llvm/CodeGen/TargetFrameLowering.h
  llvm/lib/CodeGen/RegUsageInfoCollector.cpp
  llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
  llvm/lib/Target/ARM/ARMFrameLowering.h
  llvm/test/CodeGen/ARM/ipra-no-csr.ll


Index: llvm/test/CodeGen/ARM/ipra-no-csr.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/ipra-no-csr.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple armv7a--none-eabi < %s              | FileCheck %s
+; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
+
+; Other targets disable callee-saved registers for internal functions when
+; using IPRA, but that isn't profitable for ARM because the PUSH/POP
+; instructions can more efficiently save registers than using individual
+; LDR/STRs in the caller.
+
+define internal void @callee() norecurse {
+; CHECK-LABEL: callee:
+entry:
+; CHECK: push {r4, lr}
+; CHECK: pop {r4, pc}
+  tail call void asm sideeffect "", "~{r4}"()
+  ret void
+}
+
+define void @caller() {
+entry:
+  call void @callee()
+  ret void
+}
Index: llvm/lib/Target/ARM/ARMFrameLowering.h
===================================================================
--- llvm/lib/Target/ARM/ARMFrameLowering.h
+++ llvm/lib/Target/ARM/ARMFrameLowering.h
@@ -63,6 +63,11 @@
   bool enableShrinkWrapping(const MachineFunction &MF) const override {
     return true;
   }
+  bool isProfitableForNoCSROpt(const Function &F) const override {
+    // The no-CSR optimisation is bad for code size on ARM, because we can save
+    // many registers with a single PUSH/POP pair.
+    return false;
+  }
 
 private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Index: llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
===================================================================
--- llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
+++ llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
@@ -71,7 +71,9 @@
 
   // When interprocedural register allocation is enabled caller saved registers
   // are preferred over callee saved registers.
-  if (MF.getTarget().Options.EnableIPRA && isSafeForNoCSROpt(MF.getFunction()))
+  if (MF.getTarget().Options.EnableIPRA &&
+      isSafeForNoCSROpt(MF.getFunction()) &&
+      isProfitableForNoCSROpt(MF.getFunction()))
     return;
 
   // Get the callee saved register list...
Index: llvm/lib/CodeGen/RegUsageInfoCollector.cpp
===================================================================
--- llvm/lib/CodeGen/RegUsageInfoCollector.cpp
+++ llvm/lib/CodeGen/RegUsageInfoCollector.cpp
@@ -171,7 +171,8 @@
       SetRegAsDefined(PReg);
   }
 
-  if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
+  if (TargetFrameLowering::isSafeForNoCSROpt(F) &&
+      MF.getSubtarget().getFrameLowering()->isProfitableForNoCSROpt(F)) {
     ++NumCSROpt;
     LLVM_DEBUG(dbgs() << MF.getName()
                       << " function optimized for not having CSR.\n");
Index: llvm/include/llvm/CodeGen/TargetFrameLowering.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -378,6 +378,11 @@
     return true;
   }
 
+  /// Check if the no-CSR optimisation is profitable for the given function.
+  virtual bool isProfitableForNoCSROpt(const Function &F) const {
+    return true;
+  }
+
   /// Return initial CFA offset value i.e. the one valid at the beginning of the
   /// function (before any stack operations).
   virtual int getInitialCFAOffset(const MachineFunction &MF) const;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D64910.213003.patch
Type: text/x-patch
Size: 3332 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190802/dd6503ae/attachment.bin>