[llvm] r367612 - [AArch64][x86] adjust tests with shift-add-shift; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Thu Aug  1 14:08:08 2019
New Revision: 367612

URL: http://llvm.org/viewvc/llvm-project?rev=367612&view=rev
Log:
[AArch64][x86] adjust tests with shift-add-shift; NFC

Prevent folding away the math completely.

Modified:
    llvm/trunk/test/CodeGen/AArch64/shift-mod.ll
    llvm/trunk/test/CodeGen/X86/shift-combine.ll

Modified: llvm/trunk/test/CodeGen/AArch64/shift-mod.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/shift-mod.ll?rev=367612&r1=367611&r2=367612&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/shift-mod.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/shift-mod.ll Thu Aug  1 14:08:08 2019
@@ -91,10 +91,12 @@ define i64 @ashr_add_shl_i32(i64 %r) {
 define i64 @ashr_add_shl_i8(i64 %r) {
 ; CHECK-LABEL: ashr_add_shl_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb x0, w0
+; CHECK-NEXT:    mov x8, #72057594037927936
+; CHECK-NEXT:    add x8, x8, x0, lsl #56
+; CHECK-NEXT:    asr x0, x8, #56
 ; CHECK-NEXT:    ret
   %conv = shl i64 %r, 56
-  %sext = add i64 %conv, 4294967296
+  %sext = add i64 %conv, 72057594037927936
   %conv1 = ashr i64 %sext, 56
   ret i64 %conv1
 }

Modified: llvm/trunk/test/CodeGen/X86/shift-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-combine.ll?rev=367612&r1=367611&r2=367612&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-combine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-combine.ll Thu Aug  1 14:08:08 2019
@@ -182,17 +182,23 @@ define i64 @ashr_add_shl_i32(i64 %r) nou
 define i64 @ashr_add_shl_i8(i64 %r) nounwind {
 ; X32-LABEL: ashr_add_shl_i8:
 ; X32:       # %bb.0:
-; X32-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movl %eax, %edx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    shll $24, %edx
+; X32-NEXT:    addl $16777216, %edx # imm = 0x1000000
+; X32-NEXT:    movl %edx, %eax
+; X32-NEXT:    sarl $24, %eax
 ; X32-NEXT:    sarl $31, %edx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ashr_add_shl_i8:
 ; X64:       # %bb.0:
-; X64-NEXT:    movsbq %dil, %rax
+; X64-NEXT:    shlq $56, %rdi
+; X64-NEXT:    movabsq $72057594037927936, %rax # imm = 0x100000000000000
+; X64-NEXT:    addq %rdi, %rax
+; X64-NEXT:    sarq $56, %rax
 ; X64-NEXT:    retq
   %conv = shl i64 %r, 56
-  %sext = add i64 %conv, 4294967296
+  %sext = add i64 %conv, 72057594037927936
   %conv1 = ashr i64 %sext, 56
   ret i64 %conv1
 }