[llvm] r367607 - [AArch64][x86] add tests for shift-add-shift; NFC (PR42644)
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 1 13:32:27 PDT 2019
Author: spatel
Date: Thu Aug 1 13:32:27 2019
New Revision: 367607
URL: http://llvm.org/viewvc/llvm-project?rev=367607&view=rev
Log:
[AArch64][x86] add tests for shift-add-shift; NFC (PR42644)
Modified:
llvm/trunk/test/CodeGen/AArch64/shift-mod.ll
llvm/trunk/test/CodeGen/X86/shift-combine.ll
Modified: llvm/trunk/test/CodeGen/AArch64/shift-mod.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/shift-mod.ll?rev=367607&r1=367606&r2=367607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/shift-mod.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/shift-mod.ll Thu Aug 1 13:32:27 2019
@@ -72,3 +72,80 @@ entry:
%shr = shl i64 %y, %sh_prom
ret i64 %shr
}
+
+; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644
+
+define i64 @ashr_add_shl_i32(i64 %r) {
+; CHECK-LABEL: ashr_add_shl_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4294967296
+; CHECK-NEXT: add x8, x8, x0, lsl #32
+; CHECK-NEXT: asr x0, x8, #32
+; CHECK-NEXT: ret
+ %conv = shl i64 %r, 32
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 32
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_i8(i64 %r) {
+; CHECK-LABEL: ashr_add_shl_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sxtb x0, w0
+; CHECK-NEXT: ret
+ %conv = shl i64 %r, 56
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 56
+ ret i64 %conv1
+}
+
+define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) {
+; CHECK-LABEL: ashr_add_shl_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl v0.4s, v0.4s, #24
+; CHECK-NEXT: movi v1.4s, #1, lsl #24
+; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: sshr v0.4s, v0.4s, #24
+; CHECK-NEXT: ret
+ %conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
+ %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
+ %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
+ ret <4 x i32> %conv1
+}
+
+define i64 @ashr_add_shl_i36(i64 %r) {
+; CHECK-LABEL: ashr_add_shl_i36:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx x0, x0, #0, #28
+; CHECK-NEXT: ret
+ %conv = shl i64 %r, 36
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 36
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) {
+; CHECK-LABEL: ashr_add_shl_mismatch_shifts1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4294967296
+; CHECK-NEXT: add x8, x8, x0, lsl #8
+; CHECK-NEXT: asr x0, x8, #32
+; CHECK-NEXT: ret
+ %conv = shl i64 %r, 8
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 32
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) {
+; CHECK-LABEL: ashr_add_shl_mismatch_shifts2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #4294967296
+; CHECK-NEXT: add x8, x8, x0, lsr #8
+; CHECK-NEXT: lsr x0, x8, #8
+; CHECK-NEXT: ret
+ %conv = lshr i64 %r, 8
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 8
+ ret i64 %conv1
+}
Modified: llvm/trunk/test/CodeGen/X86/shift-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-combine.ll?rev=367607&r1=367606&r2=367607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-combine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-combine.ll Thu Aug 1 13:32:27 2019
@@ -154,3 +154,156 @@ define i32* @test_exact6(i32 %a, i32 %b,
%gep = getelementptr inbounds i32, i32* %x, i32 %shr
ret i32* %gep
}
+
+; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=42644
+
+define i64 @ashr_add_shl_i32(i64 %r) nounwind {
+; X32-LABEL: ashr_add_shl_i32:
+; X32: # %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: incl %eax
+; X32-NEXT: movl %eax, %edx
+; X32-NEXT: sarl $31, %edx
+; X32-NEXT: retl
+;
+; X64-LABEL: ashr_add_shl_i32:
+; X64: # %bb.0:
+; X64-NEXT: shlq $32, %rdi
+; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000
+; X64-NEXT: addq %rdi, %rax
+; X64-NEXT: sarq $32, %rax
+; X64-NEXT: retq
+ %conv = shl i64 %r, 32
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 32
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_i8(i64 %r) nounwind {
+; X32-LABEL: ashr_add_shl_i8:
+; X32: # %bb.0:
+; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl %eax, %edx
+; X32-NEXT: sarl $31, %edx
+; X32-NEXT: retl
+;
+; X64-LABEL: ashr_add_shl_i8:
+; X64: # %bb.0:
+; X64-NEXT: movsbq %dil, %rax
+; X64-NEXT: retq
+ %conv = shl i64 %r, 56
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 56
+ ret i64 %conv1
+}
+
+define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) nounwind {
+; X32-LABEL: ashr_add_shl_v4i8:
+; X32: # %bb.0:
+; X32-NEXT: pushl %edi
+; X32-NEXT: pushl %esi
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X32-NEXT: shll $24, %edi
+; X32-NEXT: shll $24, %esi
+; X32-NEXT: shll $24, %edx
+; X32-NEXT: shll $24, %ecx
+; X32-NEXT: addl $16777216, %ecx # imm = 0x1000000
+; X32-NEXT: addl $16777216, %edx # imm = 0x1000000
+; X32-NEXT: addl $16777216, %esi # imm = 0x1000000
+; X32-NEXT: addl $16777216, %edi # imm = 0x1000000
+; X32-NEXT: sarl $24, %edi
+; X32-NEXT: sarl $24, %esi
+; X32-NEXT: sarl $24, %edx
+; X32-NEXT: sarl $24, %ecx
+; X32-NEXT: movl %ecx, 12(%eax)
+; X32-NEXT: movl %edx, 8(%eax)
+; X32-NEXT: movl %esi, 4(%eax)
+; X32-NEXT: movl %edi, (%eax)
+; X32-NEXT: popl %esi
+; X32-NEXT: popl %edi
+; X32-NEXT: retl $4
+;
+; X64-LABEL: ashr_add_shl_v4i8:
+; X64: # %bb.0:
+; X64-NEXT: pslld $24, %xmm0
+; X64-NEXT: paddd {{.*}}(%rip), %xmm0
+; X64-NEXT: psrad $24, %xmm0
+; X64-NEXT: retq
+ %conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>
+ %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
+ %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>
+ ret <4 x i32> %conv1
+}
+
+define i64 @ashr_add_shl_i36(i64 %r) nounwind {
+; X32-LABEL: ashr_add_shl_i36:
+; X32: # %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT: shll $4, %edx
+; X32-NEXT: movl %edx, %eax
+; X32-NEXT: sarl $4, %eax
+; X32-NEXT: sarl $31, %edx
+; X32-NEXT: retl
+;
+; X64-LABEL: ashr_add_shl_i36:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: shlq $36, %rax
+; X64-NEXT: sarq $36, %rax
+; X64-NEXT: retq
+ %conv = shl i64 %r, 36
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 36
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) nounwind {
+; X32-LABEL: ashr_add_shl_mismatch_shifts1:
+; X32: # %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: incl %eax
+; X32-NEXT: movl %eax, %edx
+; X32-NEXT: sarl $31, %edx
+; X32-NEXT: retl
+;
+; X64-LABEL: ashr_add_shl_mismatch_shifts1:
+; X64: # %bb.0:
+; X64-NEXT: shlq $8, %rdi
+; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000
+; X64-NEXT: addq %rdi, %rax
+; X64-NEXT: sarq $32, %rax
+; X64-NEXT: retq
+ %conv = shl i64 %r, 8
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 32
+ ret i64 %conv1
+}
+
+define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) nounwind {
+; X32-LABEL: ashr_add_shl_mismatch_shifts2:
+; X32: # %bb.0:
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT: shrdl $8, %edx, %eax
+; X32-NEXT: shrl $8, %edx
+; X32-NEXT: incl %edx
+; X32-NEXT: shrdl $8, %edx, %eax
+; X32-NEXT: shrl $8, %edx
+; X32-NEXT: retl
+;
+; X64-LABEL: ashr_add_shl_mismatch_shifts2:
+; X64: # %bb.0:
+; X64-NEXT: shrq $8, %rdi
+; X64-NEXT: movabsq $4294967296, %rax # imm = 0x100000000
+; X64-NEXT: addq %rdi, %rax
+; X64-NEXT: shrq $8, %rax
+; X64-NEXT: retq
+ %conv = lshr i64 %r, 8
+ %sext = add i64 %conv, 4294967296
+ %conv1 = ashr i64 %sext, 8
+ ret i64 %conv1
+}
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