[PATCH] D65580: [ARM] Tighten up VLDRH.32 with low alignments

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, samparker, SjoerdMeijer, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

VLDRH needs to have an alignment of at least 2, including the widening/narrowing versions. This tightens up the ISel patterns for it and alters allowsMisalignedMemoryAccesses so that unaligned accesses are expanded through the stack. It also fixed some incorrect shift amounts, which seemed to be passing a multiple not a shift.


https://reviews.llvm.org/D65580

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-ldst-offset.ll
  llvm/test/CodeGen/Thumb2/mve-ldst-postinc.ll
  llvm/test/CodeGen/Thumb2/mve-ldst-preinc.ll
  llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D65580.212793.patch
Type: text/x-patch
Size: 18138 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190801/e8014fa0/attachment.bin>