[llvm] r367556 - [X86] EltsFromConsecutiveLoads - don't attempt to merge volatile loads (PR42846)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Aug  1 06:13:18 2019
New Revision: 367556

URL: http://llvm.org/viewvc/llvm-project?rev=367556&view=rev
Log:
[X86] EltsFromConsecutiveLoads - don't attempt to merge volatile loads (PR42846)

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=367556&r1=367555&r2=367556&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Aug  1 06:13:18 2019
@@ -7572,7 +7572,10 @@ static SDValue LowerAsSplatVectorLoad(SD
 // Recurse to find a LoadSDNode source and the accumulated ByteOffest.
 static bool findEltLoadSrc(SDValue Elt, LoadSDNode *&Ld, int64_t &ByteOffset) {
   if (ISD::isNON_EXTLoad(Elt.getNode())) {
-    Ld = cast<LoadSDNode>(Elt);
+    auto *BaseLd = cast<LoadSDNode>(Elt);
+    if (BaseLd->getMemOperand()->getFlags() & MachineMemOperand::MOVolatile)
+      return false;
+    Ld = BaseLd;
     ByteOffset = 0;
     return true;
   }

Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll?rev=367556&r1=367555&r2=367556&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll Thu Aug  1 06:13:18 2019
@@ -666,3 +666,32 @@ define <16 x i16> @merge_16i16_i16_0uu3z
   %resF = insertelement <16 x i16> %resE, i16 %valF, i16 15
   ret <16 x i16> %resF
 }
+
+;
+; Volatile tests.
+;
+
+ at l = external global <32 x i8>, align 32
+
+define <2 x i8> @PR42846(<2 x i8>* %j, <2 x i8> %k) {
+; AVX-LABEL: PR42846:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vmovdqa {{.*}}(%rip), %ymm1
+; AVX-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
+; AVX-NEXT:    vpextrw $0, %xmm1, (%rdi)
+; AVX-NEXT:    vzeroupper
+; AVX-NEXT:    retq
+;
+; X32-AVX-LABEL: PR42846:
+; X32-AVX:       # %bb.0:
+; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-AVX-NEXT:    vmovdqa l, %ymm1
+; X32-AVX-NEXT:    vpmovzxbq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
+; X32-AVX-NEXT:    vpextrw $0, %xmm1, (%eax)
+; X32-AVX-NEXT:    vzeroupper
+; X32-AVX-NEXT:    retl
+  %t0 = load volatile <32 x i8>, <32 x i8>* @l, align 32
+  %shuffle = shufflevector <32 x i8> %t0, <32 x i8> undef, <2 x i32> <i32 0, i32 1>
+  store <2 x i8> %shuffle, <2 x i8>* %j, align 2
+  ret <2 x i8> %shuffle
+}