[PATCH] D65497: [RISCV] Avoid generating AssertZext for RV64 when lowering floating Libcall

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


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Comment at: test/CodeGen/RISCV/rv32i-rv64i-float-double.ll:39
+; RV64IF-NEXT:    slli a1, s0, 32
+; RV64IF-NEXT:    srli a1, a1, 32
 ; RV64IF-NEXT:    call __divsf3
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Why this two extension is not gone? I thought this patch should also improve divsf3 too?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65497/new/

https://reviews.llvm.org/D65497