[PATCH] D65554: Prevent vregs leaking into the MC layer via TargetRegisterClass::contains()

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:90-91
   bool contains(unsigned Reg) const {
+    if (!Register::isPhysicalRegister(Reg))
+      return false;
     return MC->contains(Reg);
----------------
dsanders wrote:
> arsenm wrote:
> > I think this should be a hard assert. Any of the users of this almost certainly do not intend to reach this
> Unfortunately they do expect it at the moment. This is what happens when you make it a hard assert:
> ```
>   Expected Passes    : 31313
>   Expected Failures  : 154
>   Unsupported Tests  : 435
>   Unexpected Failures: 894
> ```
> It affects Hexagon, X86, ARM, AMDGPU, and AArch64 primarily.
Should add a FIXME


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65554/new/

https://reviews.llvm.org/D65554