[PATCH] D65500: [RISCV] Support 'f' Inline Assembly Constraint

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: asb, lewis-revill.
Herald added subscribers: llvm-commits, cfe-commits, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added projects: clang, LLVM.

This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D65500

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/riscv-inline-asm.c
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-invalid.ll

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