[PATCH] D65389: [AArch64][SVE2] Use destination register as source register

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

The changes are non-functional for the assembler/disassembler, but are genuine fixes to the instructions that are needed when the instructions will be used for codegen.



================
Comment at: lib/Target/AArch64/SVEInstrFormats.td:2696
+
+  let Constraints = "$Zd = $_Zd";
+}
----------------
It's worth pointing out (possibly also in the commit message) for these top/bottom instructions that the bottom ones are not destructive (they zero out the odd lanes), whereas the top ones are destructive (they leave the even lanes in-tact).


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Comment at: lib/Target/AArch64/SVEInstrFormats.td:2725
+  let Inst{12-11} = opc; // S, R
+  let Inst{10}    = 0b0;
   let Inst{9-5}   = Zn;
----------------
nit: // Top ?


================
Comment at: lib/Target/AArch64/SVEInstrFormats.td:2749
+  let Inst{12-11} = opc; // S, R
+  let Inst{10}    = 0b1;
+  let Inst{9-5}   = Zn;
----------------
nit: // Top ?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D65389/new/

https://reviews.llvm.org/D65389