[PATCH] D65447: GlobalISel: Lower scalarizing unmerge of a vector to shifts

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: aemerson, aditya_nandakumar, paquette, dsanders.
Herald added subscribers: Petar.Avramovic, volkan, tpr, rovka, nhaehnle, wdng, jvesely.

AMDGPU sometimes has legal s16 and <2 x s16> operations, but all
registers are really 32-bit. An unmerge destination really should ben
widened to a 32-bit register. If widening a scalarizing vector with a
target size that matches the vector size, bitcast to integer and
extract the relevant bits with shifts.

      

I'm not sure if this is the right place for this. This could arguably
be part of widenScalar for the result. I also have a growing feeling
that we're missing a bitcast legalize action.


https://reviews.llvm.org/D65447

Files:
  include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

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