[PATCH] D65442: [AArch64] Update MTE system register encodings

Tue Jul 30 06:06:31 PDT 2019

LukeCheeseman created this revision.
LukeCheeseman added reviewers: pbarrio, momchil.velikov, miyuki, MarkMurrayARM, labrinea, simon_tatham.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

- The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3 and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6 as per https://developer.arm.com/docs/ddi0487/latest.

Repository:
  rL LLVM

https://reviews.llvm.org/D65442

Files:
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/test/MC/AArch64/armv8.5a-mte.s
  llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

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