[llvm] r367296 - [ARM][LowOverheadLoops] Revert non-header LE target
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 30 01:08:44 PDT 2019
Author: sam_parker
Date: Tue Jul 30 01:08:44 2019
New Revision: 367296
URL: http://llvm.org/viewvc/llvm-project?rev=367296&view=rev
Log:
[ARM][LowOverheadLoops] Revert non-header LE target
Revert the hardware loop upon finding a LoopEnd that doesn't target
the loop header, instead of asserting a failure.
Differential Revision: https://reviews.llvm.org/D65268
Added:
llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
Modified:
llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp?rev=367296&r1=367295&r2=367296&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLowOverheadLoops.cpp Tue Jul 30 01:08:44 2019
@@ -207,9 +207,15 @@ bool ARMLowOverheadLoops::ProcessLoop(Ma
return false;
}
- if (!End->getOperand(1).isMBB() ||
- End->getOperand(1).getMBB() != ML->getHeader())
- report_fatal_error("Expected LoopEnd to target Loop Header");
+ if (!End->getOperand(1).isMBB())
+ report_fatal_error("Expected LoopEnd to target basic block");
+
+ // TODO Maybe there's cases where the target doesn't have to be the header,
+ // but for now be safe and revert.
+ if (End->getOperand(1).getMBB() != ML->getHeader()) {
+ LLVM_DEBUG(dbgs() << "ARM Loops: LoopEnd is not targetting header.\n");
+ Revert = true;
+ }
// The WLS and LE instructions have 12-bits for the label offset. WLS
// requires a positive offset, while LE uses negative.
Added: llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir?rev=367296&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir (added)
+++ llvm/trunk/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir Tue Jul 30 01:08:44 2019
@@ -0,0 +1,255 @@
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
+# CHECK-NOT: t2DLS
+# CHECK: bb.5.for.inc16:
+# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14
+# CHECK: t2CMPri $lr, 0, 14
+# CHECK: t2Bcc %bb.6, 1
+# CHECK: tB %bb.2
+# CHECK: bb.6.for.cond4.preheader:
+
+--- |
+ define void @header_not_target_unrolled_loop(i32* nocapture %v, i32 %n) {
+ entry:
+ %cmp56 = icmp sgt i32 %n, 1
+ br i1 %cmp56, label %for.cond1.preheader.preheader, label %for.end20
+
+ for.cond1.preheader.preheader: ; preds = %entry
+ br label %for.cond1.preheader
+
+ for.cond.loopexit: ; preds = %for.inc16, %for.cond1.preheader
+ %cmp = icmp sgt i32 %gap.057.in, 3
+ br i1 %cmp, label %for.cond1.preheader, label %for.end20
+
+ for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.cond.loopexit
+ %gap.057.in = phi i32 [ %gap.057, %for.cond.loopexit ], [ %n, %for.cond1.preheader.preheader ]
+ %gap.057 = sdiv i32 %gap.057.in, 2
+ %cmp252 = icmp slt i32 %gap.057, %n
+ %tmp = sub i32 %n, %gap.057
+ call void @llvm.set.loop.iterations.i32(i32 %tmp)
+ br i1 %cmp252, label %for.cond4.preheader.preheader, label %for.cond.loopexit
+
+ for.cond4.preheader.preheader: ; preds = %for.cond1.preheader
+ %tmp2 = mul i32 %gap.057, -4
+ %tmp6 = mul i32 %gap.057, -2
+ %scevgep1 = getelementptr i32, i32* %v, i32 %gap.057
+ %0 = shl i32 %gap.057, 2
+ br label %for.cond4.preheader
+
+ for.cond4.preheader: ; preds = %for.inc16, %for.cond4.preheader.preheader
+ %lsr.iv2 = phi i32* [ %scevgep3, %for.inc16 ], [ %scevgep1, %for.cond4.preheader.preheader ]
+ %lsr.iv = phi i32* [ %v, %for.cond4.preheader.preheader ], [ %scevgep, %for.inc16 ]
+ %i.053 = phi i32 [ %inc, %for.inc16 ], [ %gap.057, %for.cond4.preheader.preheader ]
+ %tmp8 = phi i32 [ %tmp, %for.cond4.preheader.preheader ], [ %tmp16, %for.inc16 ]
+ %j.048 = sub nsw i32 %i.053, %gap.057
+ %cmp549 = icmp sgt i32 %j.048, -1
+ br i1 %cmp549, label %land.rhs.preheader, label %for.inc16
+
+ land.rhs.preheader: ; preds = %for.cond4.preheader
+ br label %land.rhs
+
+ land.rhs: ; preds = %land.rhs.preheader, %for.body8
+ %lsr.iv4 = phi i32 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %for.body8 ]
+ %j.051 = phi i32 [ %j.0, %for.body8 ], [ %j.048, %land.rhs.preheader ]
+ %1 = bitcast i32* %lsr.iv2 to i8*
+ %2 = bitcast i32* %lsr.iv to i8*
+ %uglygep10 = getelementptr i8, i8* %2, i32 %lsr.iv4
+ %uglygep1011 = bitcast i8* %uglygep10 to i32*
+ %tmp9 = load i32, i32* %uglygep1011, align 4
+ %uglygep7 = getelementptr i8, i8* %1, i32 %lsr.iv4
+ %uglygep78 = bitcast i8* %uglygep7 to i32*
+ %tmp12 = load i32, i32* %uglygep78, align 4
+ %cmp7 = icmp sgt i32 %tmp9, %tmp12
+ br i1 %cmp7, label %for.body8, label %for.inc16
+
+ for.body8: ; preds = %land.rhs
+ %3 = bitcast i32* %lsr.iv2 to i8*
+ %4 = bitcast i32* %lsr.iv to i8*
+ %sunkaddr = getelementptr i8, i8* %4, i32 %lsr.iv4
+ %5 = bitcast i8* %sunkaddr to i32*
+ store i32 %tmp12, i32* %5, align 4
+ %uglygep = getelementptr i8, i8* %3, i32 %lsr.iv4
+ %uglygep6 = bitcast i8* %uglygep to i32*
+ store i32 %tmp9, i32* %uglygep6, align 4
+ %j.0 = sub nsw i32 %j.051, %gap.057
+ %lsr.iv.next = add i32 %lsr.iv4, %0
+ %cmp5 = icmp sgt i32 %j.0, -1
+ br i1 %cmp5, label %land.rhs, label %for.inc16
+
+ for.inc16: ; preds = %for.body8, %land.rhs, %for.cond4.preheader
+ %inc = add nsw i32 %i.053, 1
+ %scevgep = getelementptr i32, i32* %lsr.iv, i32 1
+ %tmp16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp8, i32 1)
+ %tmp17 = icmp ne i32 %tmp16, 0
+ %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1
+ br i1 %tmp17, label %for.cond4.preheader, label %for.cond.loopexit
+
+ for.end20: ; preds = %for.cond.loopexit, %entry
+ ret void
+ }
+
+ ; Function Attrs: noduplicate nounwind
+ declare void @llvm.set.loop.iterations.i32(i32) #0
+
+ ; Function Attrs: noduplicate nounwind
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+
+ ; Function Attrs: nounwind
+ declare void @llvm.stackprotector(i8*, i8**) #1
+
+ attributes #0 = { noduplicate nounwind }
+ attributes #1 = { nounwind }
+
+...
+---
+name: header_not_target_unrolled_loop
+alignment: 1
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: false
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 32
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ bb.0.entry:
+ successors: %bb.1(0x40000000), %bb.9(0x40000000)
+
+ $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
+ frame-setup CFI_INSTRUCTION def_cfa_offset 32
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r10, -8
+ frame-setup CFI_INSTRUCTION offset $r9, -12
+ frame-setup CFI_INSTRUCTION offset $r8, -16
+ frame-setup CFI_INSTRUCTION offset $r7, -20
+ frame-setup CFI_INSTRUCTION offset $r6, -24
+ frame-setup CFI_INSTRUCTION offset $r5, -28
+ frame-setup CFI_INSTRUCTION offset $r4, -32
+ tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.9, 11, killed $cpsr
+
+ bb.1:
+ successors: %bb.3(0x80000000)
+
+ $r9 = tMOVr $r1, 14, $noreg
+ tB %bb.3, 14, $noreg
+
+ bb.2.for.cond.loopexit:
+ successors: %bb.3(0x7c000000), %bb.9(0x04000000)
+
+ t2CMPri killed renamable $r12, 4, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.9, 11, killed $cpsr
+
+ bb.3.for.cond1.preheader:
+ successors: %bb.4(0x40000000), %bb.2(0x40000000)
+
+ renamable $r2 = t2ADDrs $r9, $r9, 251, 14, $noreg, $noreg
+ $r12 = tMOVr killed $r9, 14, $noreg
+ renamable $lr = t2SUBrs renamable $r1, renamable $r2, 9, 14, $noreg, $noreg
+ renamable $r9 = t2ASRri renamable $r2, 1, 14, $noreg, $noreg
+ t2CMPrs renamable $r1, killed renamable $r2, 9, 14, $noreg, implicit-def $cpsr
+ t2DoLoopStart renamable $lr
+ tBcc %bb.2, 13, killed $cpsr
+
+ bb.4.for.cond4.preheader.preheader:
+ successors: %bb.7(0x50000000), %bb.5(0x30000000)
+
+ renamable $r3 = t2ADDrs renamable $r0, renamable $r9, 18, 14, $noreg, $noreg
+ renamable $r10 = t2LSLri renamable $r9, 2, 14, $noreg, $noreg
+ $r5 = tMOVr $r0, 14, $noreg
+ $r8 = tMOVr $r9, 14, $noreg
+ renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
+ tBcc %bb.7, 5, killed $cpsr
+
+ bb.5.for.inc16:
+ successors: %bb.6(0x7c000000), %bb.2(0x04000000)
+
+ renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
+ renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 4, 14, $noreg
+ renamable $r8 = nsw t2ADDri killed renamable $r8, 1, 14, $noreg, $noreg
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.6.for.cond4.preheader:
+ successors: %bb.7(0x50000000), %bb.5(0x30000000)
+
+ renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr
+ tBcc %bb.5, 4, killed $cpsr
+
+ bb.7.land.rhs.preheader:
+ successors: %bb.8(0x80000000)
+
+ renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg
+
+ bb.8.land.rhs:
+ successors: %bb.5(0x07e00000), %bb.8(0x78200000)
+
+ renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load 4 from %ir.uglygep78)
+ renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load 4 from %ir.uglygep1011)
+ tCMPr renamable $r2, renamable $r4, 14, $noreg, implicit-def $cpsr
+ t2IT 12, 1, implicit-def $itstate
+ tSTRr killed renamable $r4, renamable $r5, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.5)
+ tSTRr killed renamable $r2, renamable $r3, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.uglygep6)
+ renamable $r6 = tADDhirr killed renamable $r6, renamable $r10, 12, $cpsr, implicit $r6, implicit $itstate
+ renamable $r7 = nsw t2SUBrr killed renamable $r7, renamable $r9, 12, $cpsr, $noreg, implicit $r7, implicit killed $itstate
+ t2IT 12, 8, implicit-def $itstate
+ t2CMPri renamable $r7, -1, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
+ tBcc %bb.8, 12, killed $cpsr
+ tB %bb.5, 14, $noreg
+
+ bb.9.for.end20:
+ $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $pc
+
+...
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