[PATCH] D65063: [PowerPC] Eliminate loads feeding swaps for vector type by using big-endian load.
Jinsong Ji via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 29 12:53:51 PDT 2019
jsji added a comment.
Mostly good to me.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13109
+
+ for (; I != E; ++I) {
+ if (*I != i)
----------------
Can this be a range-based for loop?
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13124
+
+ if (!Subtarget.hasP9Vector() && (VT == MVT::v8i16 || VT == MVT::v16i8))
+ return SDValue();
----------------
Maybe we should check this before more expensive `IsElementReverse` check?
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:462
+ /// the vector type to load vector in big-endian element order.
+ LOAD_VEC_BE,
+
----------------
This will overlap with LXVD2X above, it would be great if we can have a follow up NFC to clean up.
================
Comment at: llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll:8
+; RUN: --check-prefix=CHECK-P9
+
+define <2 x i64> @load_swap00(<2 x i64>* %vp1, <2 x i64>* %vp2) {
----------------
Can we add one RUN line to run big endian test to make sure nothing get affected?
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D65063/new/
https://reviews.llvm.org/D65063
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