[PATCH] D65145: [AArch64][SVE] Allow explicit size specifier for predicate operand

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Thanks for this change @chill. LGTM.



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:429
+  def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
+  def : InstAlias<asm # "\t$Zdn, $Pm",
+                 (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
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nit: for consistency with the rest of the file, can you group the InstAliases and move them below the definitions of the instructions?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65145/new/

https://reviews.llvm.org/D65145