[PATCH] D54296: [RISCV] Lower inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 211697.
lewis-revill added a comment.

Rebased and updated to use '0(' prefix for memory constraints.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54296/new/

https://reviews.llvm.org/D54296

Files:
  include/llvm/IR/InlineAsm.h
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/inline-asm.ll

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