[PATCH] D65218: [RISCV] Make input/output args analyzing functions public
weiwei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 24 09:20:25 PDT 2019
wwei created this revision.
wwei added reviewers: asb, lenary, lewis-revill.
wwei added a project: LLVM.
Herald added subscribers: llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
To support CallLowering for GlobalIsel, and reduce duplicated code as much as possible, we change the C++ access specifiers from `private` to `public` for `analyzeInputArgs` and `analyzeOutputArgs` functions. Thus, GlobalIsel can reuse these two functions to support call and return lowering.
Repository:
rL LLVM
https://reviews.llvm.org/D65218
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.h
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -141,13 +141,14 @@
unsigned
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
-private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,
bool IsRet) const;
void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::OutputArg> &Outs,
bool IsRet, CallLoweringInfo *CLI) const;
+
+private:
// Lower incoming arguments, copy physregs into vregs
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D65218.211523.patch
Type: text/x-patch
Size: 900 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190724/d83060d2/attachment.bin>
More information about the llvm-commits
mailing list