[llvm] r366915 - AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 24 09:05:53 PDT 2019
Author: arsenm
Date: Wed Jul 24 09:05:53 2019
New Revision: 366915
URL: http://llvm.org/viewvc/llvm-project?rev=366915&view=rev
Log:
AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts
The G_ANYEXT handling can end up reaching selectCOPY, which mutates
the instruction in place.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=366915&r1=366914&r2=366915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Wed Jul 24 09:05:53 2019
@@ -1006,6 +1006,7 @@ bool AMDGPUInstructionSelector::selectG_
BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
.addImm(0)
.addImm(Signed ? -1 : 1);
+ I.eraseFromParent();
return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
}
@@ -1020,6 +1021,7 @@ bool AMDGPUInstructionSelector::selectG_
.addImm(0) // src1_modifiers
.addImm(Signed ? -1 : 1) // src1
.addUse(SrcReg);
+ I.eraseFromParent();
return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
}
@@ -1036,6 +1038,7 @@ bool AMDGPUInstructionSelector::selectG_
BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
.addImm(Mask)
.addReg(SrcReg);
+ I.eraseFromParent();
return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
}
@@ -1045,6 +1048,7 @@ bool AMDGPUInstructionSelector::selectG_
.addReg(SrcReg)
.addImm(0) // Offset
.addImm(SrcSize); // Width
+ I.eraseFromParent();
return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
}
@@ -1057,6 +1061,7 @@ bool AMDGPUInstructionSelector::selectG_
AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16;
BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
.addReg(SrcReg);
+ I.eraseFromParent();
return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
}
@@ -1081,6 +1086,7 @@ bool AMDGPUInstructionSelector::selectG_
.addReg(ExtReg)
.addImm(SrcSize << 16);
+ I.eraseFromParent();
return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
}
@@ -1095,6 +1101,7 @@ bool AMDGPUInstructionSelector::selectG_
.addImm(SrcSize << 16);
}
+ I.eraseFromParent();
return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
}
@@ -1369,12 +1376,7 @@ bool AMDGPUInstructionSelector::select(M
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
- if (selectG_SZA_EXT(I)) {
- I.eraseFromParent();
- return true;
- }
-
- return false;
+ return selectG_SZA_EXT(I);
case TargetOpcode::G_BRCOND:
return selectG_BRCOND(I);
case TargetOpcode::G_FRAME_INDEX:
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir?rev=366915&r1=366914&r2=366915&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir Wed Jul 24 09:05:53 2019
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---
@@ -55,7 +55,8 @@ body: |
liveins: $sgpr0
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
- ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -72,7 +73,9 @@ body: |
liveins: $sgpr0
; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
- ; GCN: $sgpr0_sgpr1 = COPY %2:sreg_64_xexec
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
+ ; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_ANYEXT %1
@@ -89,7 +92,8 @@ body: |
liveins: $sgpr0
; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32
- ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s8) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -107,7 +111,8 @@ body: |
liveins: $sgpr0
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
- ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: $sgpr0 = COPY [[COPY]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ANYEXT %1
@@ -125,7 +130,9 @@ body: |
liveins: $sgpr0
; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
- ; GCN: $sgpr0_sgpr1 = COPY %2:sreg_64_xexec
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
+ ; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ANYEXT %1
@@ -163,7 +170,8 @@ body: |
liveins: $vgpr0
; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
- ; GCN: $vgpr0 = COPY %2:vgpr_32
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: $vgpr0 = COPY [[COPY]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s32) = G_ANYEXT %1
@@ -180,7 +188,8 @@ body: |
liveins: $vgpr0
; GCN-LABEL: name: anyext_vgpr_s8_to_vgpr_s32
- ; GCN: $vgpr0 = COPY %2:vgpr_32
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: $vgpr0 = COPY [[COPY]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s8) = G_TRUNC %0
%2:vgpr(s32) = G_ANYEXT %1
@@ -198,7 +207,8 @@ body: |
liveins: $vgpr0
; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
- ; GCN: $vgpr0 = COPY %2:vgpr_32
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: $vgpr0 = COPY [[COPY]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_ANYEXT %1
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