[PATCH] D65158: [AMDGPU] Add all vgpr classes to asm parser

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 211349.
rampitec retitled this revision from "[AMDGPU] Add all vgpr classes to AMDGPUOperand::isVReg()" to "[AMDGPU] Add all vgpr classes to asm parser".
rampitec edited the summary of this revision.
rampitec added a reviewer: tpr.
rampitec added a comment.

Found where it was a problem.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65158/new/

https://reviews.llvm.org/D65158

Files:
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  test/MC/AMDGPU/gfx9_asm_all.s
  test/MC/AMDGPU/mai-err.s


Index: test/MC/AMDGPU/mai-err.s
===================================================================
--- test/MC/AMDGPU/mai-err.s
+++ test/MC/AMDGPU/mai-err.s
@@ -32,10 +32,10 @@
 // GFX900: error: instruction not supported on this GPU
 
 v_mfma_f32_32x32x1f32 v[0:31], v0, v1, a[1:32]
-// GFX908: error: not a valid operand
+// GFX908: error: invalid operand for instruction
 
 v_mfma_f32_32x32x1f32 a[0:31], v0, v1, v[1:32]
-// GFX908: error: not a valid operand
+// GFX908: error: invalid operand for instruction
 
 v_mfma_f32_32x32x1f32 a[0:31], s0, v1, a[1:32]
 // GFX908: error: invalid operand for instruction
Index: test/MC/AMDGPU/gfx9_asm_all.s
===================================================================
--- test/MC/AMDGPU/gfx9_asm_all.s
+++ test/MC/AMDGPU/gfx9_asm_all.s
@@ -5977,6 +5977,9 @@
 image_load v5, v[1:4], s[8:15] dmask:0x1 d16
 // CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
 
+image_load v[0:4], v5, s[0:7] dmask:0xf unorm tfe
+// CHECK: [0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00]
+
 image_load_mip v5, v[1:4], s[8:15] dmask:0x1
 // CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
 
Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -275,8 +275,10 @@
            isRegClass(AMDGPU::VReg_64RegClassID) ||
            isRegClass(AMDGPU::VReg_96RegClassID) ||
            isRegClass(AMDGPU::VReg_128RegClassID) ||
+           isRegClass(AMDGPU::VReg_160RegClassID) ||
            isRegClass(AMDGPU::VReg_256RegClassID) ||
-           isRegClass(AMDGPU::VReg_512RegClassID);
+           isRegClass(AMDGPU::VReg_512RegClassID) ||
+           isRegClass(AMDGPU::VReg_1024RegClassID);
   }
 
   bool isVReg32() const {
@@ -1872,8 +1874,10 @@
       case 2: return AMDGPU::VReg_64RegClassID;
       case 3: return AMDGPU::VReg_96RegClassID;
       case 4: return AMDGPU::VReg_128RegClassID;
+      case 5: return AMDGPU::VReg_160RegClassID;
       case 8: return AMDGPU::VReg_256RegClassID;
       case 16: return AMDGPU::VReg_512RegClassID;
+      case 32: return AMDGPU::VReg_1024RegClassID;
     }
   } else if (Is == IS_TTMP) {
     switch (RegWidth) {


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