[llvm] r366909 - [ARM] MVE floating point compares and selects
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 24 07:28:22 PDT 2019
Author: dmgreen
Date: Wed Jul 24 07:28:22 2019
New Revision: 366909
URL: http://llvm.org/viewvc/llvm-project?rev=366909&view=rev
Log:
[ARM] MVE floating point compares and selects
Much like integers, this adds MVE floating point compares and select. It
requires a lot more buildvector/shuffle code because we may need to expand the
compares without mve.fp, and requires support for and/or because of the way we
lower llvm condition codes.
Some original code by David Sherwood
Differential Revision: https://reviews.llvm.org/D65054
Added:
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/test/CodeGen/Thumb2/mve-vpsel.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=366909&r1=366908&r2=366909&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 24 07:28:22 2019
@@ -288,6 +288,7 @@ void ARMTargetLowering::addMVEVectorType
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
+ setOperationAction(ISD::SETCC, VT, Custom);
if (HasMVEFP) {
setOperationAction(ISD::FMINNUM, VT, Legal);
@@ -346,6 +347,7 @@ void ARMTargetLowering::addMVEVectorType
setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
+ setOperationAction(ISD::SETCC, VT, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
}
}
@@ -5895,6 +5897,11 @@ static SDValue LowerVSETCC(SDValue Op, S
if (Op.getValueType().getVectorElementType() != MVT::i1)
return SDValue();
+ // Make sure we expand floating point setcc to scalar if we do not have
+ // mve.fp, so that we can handle them from there.
+ if (Op0.getValueType().isFloatingPoint() && !ST->hasMVEFloatOps())
+ return SDValue();
+
CmpVT = VT;
}
@@ -5925,7 +5932,12 @@ static SDValue LowerVSETCC(SDValue Op, S
switch (SetCCOpcode) {
default: llvm_unreachable("Illegal FP comparison");
case ISD::SETUNE:
- case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;
+ case ISD::SETNE:
+ if (ST->hasMVEFloatOps()) {
+ Opc = ARMISD::VCNE; break;
+ } else {
+ Invert = true; LLVM_FALLTHROUGH;
+ }
case ISD::SETOEQ:
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
case ISD::SETOLT:
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=366909&r1=366908&r2=366909&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Wed Jul 24 07:28:22 2019
@@ -3000,6 +3000,20 @@ multiclass unpred_vcmp_r<SDPatternOperat
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc))>;
}
+multiclass unpred_vcmpf_z<SDPatternOperator opnode, int fc> {
+ def f16 : Pat<(v8i1 (opnode (v8f16 MQPR:$v1))),
+ (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
+ def f32 : Pat<(v4i1 (opnode (v4f32 MQPR:$v1))),
+ (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
+}
+
+multiclass unpred_vcmpf_r<SDPatternOperator opnode, int fc> {
+ def f16 : Pat<(v8i1 (opnode (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
+ (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>;
+ def f32 : Pat<(v4i1 (opnode (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
+ (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc))>;
+}
+
let Predicates = [HasMVEInt] in {
defm MVE_VCEQZ : unpred_vcmp_z<ARMvceqz, "i", 0>;
defm MVE_VCNEZ : unpred_vcmp_z<ARMvcnez, "i", 1>;
@@ -3016,6 +3030,20 @@ let Predicates = [HasMVEInt] in {
defm MVE_VCGEU : unpred_vcmp_r<ARMvcgeu, "u", 2>;
}
+let Predicates = [HasMVEFloat] in {
+ defm MVE_VFCEQZ : unpred_vcmpf_z<ARMvceqz, 0>;
+ defm MVE_VFCNEZ : unpred_vcmpf_z<ARMvcnez, 1>;
+ defm MVE_VFCLEZ : unpred_vcmpf_z<ARMvclez, 13>;
+ defm MVE_VFCGTZ : unpred_vcmpf_z<ARMvcgtz, 12>;
+ defm MVE_VFCLTZ : unpred_vcmpf_z<ARMvcltz, 11>;
+ defm MVE_VFCGEZ : unpred_vcmpf_z<ARMvcgez, 10>;
+
+ defm MVE_VFCGT : unpred_vcmpf_r<ARMvcgt, 12>;
+ defm MVE_VFCGE : unpred_vcmpf_r<ARMvcge, 10>;
+ defm MVE_VFCEQ : unpred_vcmpf_r<ARMvceq, 0>;
+ defm MVE_VFCNE : unpred_vcmpf_r<ARMvcne, 1>;
+}
+
// Extra "worst case" and/or/xor partterns, going into and out of GRP
multiclass two_predops<SDPatternOperator opnode, Instruction insn> {
@@ -4457,6 +4485,11 @@ let Predicates = [HasMVEInt] in {
def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
(v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
+ def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
+ (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
+ def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
+ (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0, VCCR:$pred))>;
+
def : Pat<(v16i8 (vselect (v16i8 MQPR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
(v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0,
(MVE_VCMPi8 (v16i8 MQPR:$pred), (MVE_VMOVimmi8 0), 1)))>;
@@ -4467,6 +4500,13 @@ let Predicates = [HasMVEInt] in {
(v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0,
(MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), 1)))>;
+ def : Pat<(v8f16 (vselect (v8i16 MQPR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
+ (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0,
+ (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), 1)))>;
+ def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
+ (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, 0,
+ (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), 1)))>;
+
def : Pat<(v16i8 (zext (v16i1 VCCR:$pred))),
(v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), 0, VCCR:$pred))>;
def : Pat<(v8i16 (zext (v8i1 VCCR:$pred))),
Added: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll?rev=366909&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll Wed Jul 24 07:28:22 2019
@@ -0,0 +1,3441 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oeq <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_one_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r3, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp one <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ogt <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_oge_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oge <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_olt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp olt <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ole_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q1, q0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ole <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r3, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ueq <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_une_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp une <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q1, q0
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ugt <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_uge_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uge <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ult_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ult <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ule_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ule <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ord_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ord <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_uno_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uno <4 x float> %src, %src2
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmp.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oeq <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_one_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vcmp.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp one <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ogt <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_oge_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oge <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_olt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp olt <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ole_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ole <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vcmp.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ueq <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_une_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmp.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmp.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp une <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ugt <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_uge_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uge <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ult_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ult <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ule_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ule <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ord_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ord <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_uno_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[1]
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[1]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r3, q0[0]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[0]
+; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
+; CHECK-MVE-NEXT: vmov s16, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q3[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s18, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r2, s16
+; CHECK-MVE-NEXT: vmov.16 q4[0], r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q4[1], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[2]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[3]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: vmov.16 q4[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[3]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[4]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: vmov.16 q4[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[4]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[5]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: vmov.16 q4[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[5]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[6]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: vmov.16 q4[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[6]
+; CHECK-MVE-NEXT: vmov s20, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
+; CHECK-MVE-NEXT: vmov s20, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q3[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s22, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[7]
+; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vmov r1, s20
+; CHECK-MVE-NEXT: vmov.16 q4[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q3[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q4[7], r0
+; CHECK-MVE-NEXT: vmov q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uno <8 x half> %src, %src2
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
Added: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll?rev=366909&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll Wed Jul 24 07:28:22 2019
@@ -0,0 +1,3225 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oeq <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_one_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r3, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp one <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ogt <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_oge_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oge <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_olt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp olt <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ole_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ole <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r3, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: mov.w r0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ueq <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_une_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp une <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ugt <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_uge_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uge <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ult_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ult <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ule_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ule <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_ord_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ord <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
+; CHECK-MVE-LABEL: vcmp_uno_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s0, s0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r2, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: mov.w r3, #0
+; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r3, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r3, #1
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r3, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f32 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uno <4 x float> %src, zeroinitializer
+ %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %s
+}
+
+
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmp.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oeq <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_one_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmp.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp one <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it gt
+; CHECK-MVE-NEXT: movgt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ogt <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_oge_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ge
+; CHECK-MVE-NEXT: movge r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp oge <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_olt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: movmi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp olt <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ole_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: movls r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ole <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r2, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r1, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmp.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it eq
+; CHECK-MVE-NEXT: moveq r0, #1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ueq <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_une_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmp.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmp.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp une <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: movhi r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ugt <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_uge_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: movpl r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uge <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ult_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: movlt r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ult <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ule_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: movle r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
+; CHECK-MVEFP-NEXT: movw r0, #65535
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ule <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_ord_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vc
+; CHECK-MVE-NEXT: movvc r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp ord <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
+
+define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
+; CHECK-MVE-LABEL: vcmp_uno_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[0]
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[0]
+; CHECK-MVE-NEXT: vmov s12, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[0]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s14, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q0[1]
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov.u16 r3, q1[1]
+; CHECK-MVE-NEXT: vmov r1, s12
+; CHECK-MVE-NEXT: movs r0, #0
+; CHECK-MVE-NEXT: vmov s12, r2
+; CHECK-MVE-NEXT: movs r2, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
+; CHECK-MVE-NEXT: vmov s12, r3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #1
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vmov.u16 r3, q2[1]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r2, #1
+; CHECK-MVE-NEXT: vmov s14, r3
+; CHECK-MVE-NEXT: cmp r2, #0
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vmov r2, s12
+; CHECK-MVE-NEXT: vmov.16 q3[0], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[2]
+; CHECK-MVE-NEXT: vmov.16 q3[1], r2
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[2]
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[2]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[3]
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[2], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[3]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[3]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[4]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[3], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[4]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[4]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[5]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[4], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[5]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[5]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q1[6]
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[5], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[6]
+; CHECK-MVE-NEXT: vmov s16, r1
+; CHECK-MVE-NEXT: movs r1, #0
+; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
+; CHECK-MVE-NEXT: vmov s16, r2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #1
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vmov.u16 r2, q2[6]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r1, #1
+; CHECK-MVE-NEXT: vmov s18, r2
+; CHECK-MVE-NEXT: cmp r1, #0
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmov r1, s16
+; CHECK-MVE-NEXT: vmov.16 q3[6], r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q0[7]
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmov.u16 r1, q1[7]
+; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov.u16 r1, q2[7]
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: movne r0, #1
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.16 q3[7], r0
+; CHECK-MVE-NEXT: vmov q0, q3
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x0
+; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q3
+; CHECK-MVEFP-NEXT: vmrs r0, p0
+; CHECK-MVEFP-NEXT: vcmp.f16 gt, q3, q0
+; CHECK-MVEFP-NEXT: vmrs r1, p0
+; CHECK-MVEFP-NEXT: orrs r0, r1
+; CHECK-MVEFP-NEXT: movw r1, #65535
+; CHECK-MVEFP-NEXT: eors r0, r1
+; CHECK-MVEFP-NEXT: vmsr p0, r0
+; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %c = fcmp uno <8 x half> %src, zeroinitializer
+ %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
+ ret <8 x half> %s
+}
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vpsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vpsel.ll?rev=366909&r1=366908&r2=366909&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vpsel.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vpsel.ll Wed Jul 24 07:28:22 2019
@@ -37,6 +37,30 @@ entry:
ret <4 x i32> %1
}
+define arm_aapcs_vfpcc <8 x half> @vpsel_f16(<8 x i1> *%mask, <8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: vpsel_f16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldr p0, [r0]
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = load <8 x i1>, <8 x i1>* %mask, align 4
+ %1 = select <8 x i1> %0, <8 x half> %src1, <8 x half> %src2
+ ret <8 x half> %1
+}
+
+define arm_aapcs_vfpcc <4 x float> @vpsel_f32(<4 x i1> *%mask, <4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: vpsel_f32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldr p0, [r0]
+; CHECK-NEXT: vpsel q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = load <4 x i1>, <4 x i1>* %mask, align 4
+ %1 = select <4 x i1> %0, <4 x float> %src1, <4 x float> %src2
+ ret <4 x float> %1
+}
+
define arm_aapcs_vfpcc <4 x i32> @foo(<4 x i32> %vec.ind) {
; CHECK-LABEL: foo:
; CHECK: @ %bb.0:
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