[llvm] r366854 - [GlobalISel][AArch64] Save a copy on G_SELECT by fixing condition to GPR
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 23 14:39:50 PDT 2019
Author: paquette
Date: Tue Jul 23 14:39:50 2019
New Revision: 366854
URL: http://llvm.org/viewvc/llvm-project?rev=366854&view=rev
Log:
[GlobalISel][AArch64] Save a copy on G_SELECT by fixing condition to GPR
The condition can never be fed by FPRs, so it should always be on a GPR.
Differential Revision: https://reviews.llvm.org/D65157
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=366854&r1=366853&r2=366854&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Tue Jul 23 14:39:50 2019
@@ -702,11 +702,10 @@ AArch64RegisterBankInfo::getInstrMapping
break;
// If we're taking in vectors, we have no choice but to put everything on
- // FPRs.
+ // FPRs, except for the condition. The condition must always be on a GPR.
LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
if (SrcTy.isVector()) {
- for (unsigned Idx = 0; Idx < 4; ++Idx)
- OpRegBankIdx[Idx] = PMI_FirstFPR;
+ OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR, PMI_FirstFPR, PMI_FirstFPR};
break;
}
@@ -750,8 +749,7 @@ AArch64RegisterBankInfo::getInstrMapping
// If we have more FP constraints than not, then move everything over to
// FPR.
if (NumFP >= 2)
- for (unsigned Idx = 0; Idx < 4; ++Idx)
- OpRegBankIdx[Idx] = PMI_FirstFPR;
+ OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR, PMI_FirstFPR, PMI_FirstFPR};
break;
}
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir?rev=366854&r1=366853&r2=366854&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir Tue Jul 23 14:39:50 2019
@@ -91,9 +91,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[SITOFP]]
+ ; CHECK: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[SITOFP]]
; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %3(s32)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir?rev=366854&r1=366853&r2=366854&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-select.mir Tue Jul 23 14:39:50 2019
@@ -18,8 +18,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
; CHECK: $s0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $s0
%3:_(s32) = COPY $w0
@@ -47,8 +46,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
; CHECK: $d0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $d0
%3:_(s32) = COPY $w0
@@ -75,8 +73,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
@@ -110,9 +107,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
- ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY4]]
+ ; CHECK: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
+ ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
; CHECK: $d0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $d0
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