[PATCH] D65157: [GlobalISel][AArch64] Save a copy on G_SELECT by fixing condition to GPR

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

The condition can never be fed by FPRs, so it should always be on a GPR.


https://reviews.llvm.org/D65157

Files:
  llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
@@ -18,8 +18,7 @@
     ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
     ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
-    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
-    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: $s0 = COPY [[SELECT]](s32)
     ; CHECK: RET_ReallyLR implicit $s0
     %3:_(s32) = COPY $w0
@@ -47,8 +46,7 @@
     ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
-    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
-    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: $d0 = COPY [[SELECT]](s64)
     ; CHECK: RET_ReallyLR implicit $d0
     %3:_(s32) = COPY $w0
@@ -75,8 +73,7 @@
     ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
-    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
-    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY2]]
+    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
     ; CHECK: $x0 = COPY [[SELECT]](s64)
     ; CHECK: RET_ReallyLR implicit $x0
 
@@ -110,9 +107,8 @@
     ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
     ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
     ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
-    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
-    ; CHECK: [[COPY4:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
-    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY3]](s1), [[COPY1]], [[COPY4]]
+    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
+    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
     ; CHECK: $d0 = COPY [[SELECT]](s64)
     ; CHECK: RET_ReallyLR implicit $d0
 
Index: llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
@@ -91,9 +91,8 @@
     ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $w2
     ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[COPY1]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s1) = COPY [[TRUNC]](s1)
-    ; CHECK: [[COPY4:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
-    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[SITOFP]]
+    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s32) = COPY [[COPY2]](s32)
+    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[SITOFP]]
     ; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[SELECT]](s32)
     %0:_(s32) = COPY $w0
     %1:_(s1) = G_TRUNC %3(s32)
Index: llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -702,11 +702,10 @@
       break;
 
     // If we're taking in vectors, we have no choice but to put everything on
-    // FPRs.
+    // FPRs, except for the condition. The condition must always be on a GPR.
     LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
     if (SrcTy.isVector()) {
-      for (unsigned Idx = 0; Idx < 4; ++Idx)
-        OpRegBankIdx[Idx] = PMI_FirstFPR;
+      OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR, PMI_FirstFPR, PMI_FirstFPR};
       break;
     }
 
@@ -750,8 +749,7 @@
     // If we have more FP constraints than not, then move everything over to
     // FPR.
     if (NumFP >= 2)
-      for (unsigned Idx = 0; Idx < 4; ++Idx)
-        OpRegBankIdx[Idx] = PMI_FirstFPR;
+      OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR, PMI_FirstFPR, PMI_FirstFPR};
 
     break;
   }


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