[PATCH] D65119: [GlobalISel][AArch64] Teach GISel to handle shifts in load addressing modes

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

When we select the XRO variants of loads, we can pull in very specific shifts (of the size of an element). E.g.

  ldr x1, [x2, x3, lsl #3]

This teaches GISel to handle these when they're coming from shifts specifically.

This adds a new addressing mode function, `selectAddrModeShiftedExtendXReg` which recognizes this pattern.

This also packs this up with `selectAddrModeRegisterOffset` into `selectAddrModeXRO`. This is intended to be equivalent to `selectAddrModeXRO` in AArch64ISelDAGtoDAG.

Also update load-addressing-modes to show that all of the cases here work.


https://reviews.llvm.org/D65119

Files:
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

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