[llvm] r366751 - [InstSimplify][NFC] Tests for skipping 'div-by-0' checks before @llvm.umul.with.overflow
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 22 15:09:11 PDT 2019
Author: lebedevri
Date: Mon Jul 22 15:09:11 2019
New Revision: 366751
URL: http://llvm.org/viewvc/llvm-project?rev=366751&view=rev
Log:
[InstSimplify][NFC] Tests for skipping 'div-by-0' checks before @llvm.umul.with.overflow
These may remain after @llvm.umul.with.overflow was canonicalized
from the code that was originally doing the check via division.
Added:
llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov.ll
llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov.ll
Added: llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov.ll?rev=366751&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-smul_ov.ll Mon Jul 22 15:09:11 2019
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instsimplify -S | FileCheck %s
+
+declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #1
+
+define i1 @t0_smul(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @t0_smul(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[SMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = and i1 %smul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @t1_commutative(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @t1_commutative(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[SMUL_OV]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = and i1 %cmp, %smul.ov ; swapped
+ ret i1 %and
+}
+
+define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
+; CHECK-LABEL: @n2_wrong_size(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE1:%.*]], 0
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[SMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size1, 0 ; not %size0
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = and i1 %smul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n3_wrong_pred(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[SMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp eq i4 %size, 0 ; not 'ne'
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = and i1 %smul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @n4_not_and(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n4_not_and(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = or i1 [[SMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = or i1 %smul.ov, %cmp ; not 'and'
+ ret i1 %and
+}
+
+define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n5_not_zero(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 1
+; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[SMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 1 ; should be '0'
+ %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %smul.ov = extractvalue { i4, i1 } %smul, 1
+ %and = and i1 %smul.ov, %cmp
+ ret i1 %and
+}
Added: llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov.ll?rev=366751&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/div-by-0-guard-before-umul_ov.ll Mon Jul 22 15:09:11 2019
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instsimplify -S | FileCheck %s
+
+declare { i4, i1 } @llvm.umul.with.overflow.i4(i4, i4) #1
+
+define i1 @t0_umul(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @t0_umul(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[UMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = and i1 %umul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @t1_commutative(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @t1_commutative(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[CMP]], [[UMUL_OV]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = and i1 %cmp, %umul.ov ; swapped
+ ret i1 %and
+}
+
+define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
+; CHECK-LABEL: @n2_wrong_size(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE1:%.*]], 0
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[UMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size1, 0 ; not %size0
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size0, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = and i1 %umul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n3_wrong_pred(
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[UMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp eq i4 %size, 0 ; not 'ne'
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = and i1 %umul.ov, %cmp
+ ret i1 %and
+}
+
+define i1 @n4_not_and(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n4_not_and(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = or i1 [[UMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 0
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = or i1 %umul.ov, %cmp ; not 'and'
+ ret i1 %and
+}
+
+define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
+; CHECK-LABEL: @n5_not_zero(
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 1
+; CHECK-NEXT: [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
+; CHECK-NEXT: [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[UMUL_OV]], [[CMP]]
+; CHECK-NEXT: ret i1 [[AND]]
+;
+ %cmp = icmp ne i4 %size, 1 ; should be '0'
+ %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
+ %umul.ov = extractvalue { i4, i1 } %umul, 1
+ %and = and i1 %umul.ov, %cmp
+ ret i1 %and
+}
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