[PATCH] D65052: [ARM] MVE predicate register support

[Dave Green via Phabricator via llvm-commits]

dmgreen marked 6 inline comments as done.
dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:7385
+  SDValue AllOnes =
+      DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), dl, MVT::i32);
+  AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v16i8, AllOnes);
----------------
SjoerdMeijer wrote:
> is it weird to call `createNEONModImm` here?
It was never renamed, and the same between Neon and MVE (it was used in the VMOVimm code too.)

I can rename it easily enough. createVModImm sound OK?


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:7408
+  SDValue RecastV1;
+  // If the real predicate is not v16i1 then we need to recast this to a
+  // v16i1. This cannot be done with an ordinary bitcast because the sizes
----------------
SjoerdMeijer wrote:
> what do you mean with the "real predicate"?
The predicate may be a v4i1 or a v8i1. We cast it to a v16i1 to get the types right, using the principle that a v4i1 of abcd and a v16i1 of aaaabbbbccccdddd are the same thing.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65052/new/

https://reviews.llvm.org/D65052