[PATCH] D65094: [PowerPC] Combine address computation to favour selecting DForm instructions
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 22 07:47:30 PDT 2019
nemanjai created this revision.
nemanjai added reviewers: hfinkel, echristo, jsji, stefanp.
Herald added subscribers: shchenz, wuzish, mgrang, MaskRay, kbarton.
Herald added a project: LLVM.
When selecting a memory operation for which the only available D-Form instructions have alignment requirements for the displacement immediate, we end up having to select X-Form instructions if the immediate isn't a required multiple. However, if the base register is used for multiple memory operations, we don't need to be so pessimistic.
For example,
vector int test(char *Ptr) {
vector int a = *(vector int *)(Ptr+7);
vector int b = *(vector int *)(Ptr+23);
vector int c = *(vector int *)(Ptr+39);
vector int d = *(vector int *)(Ptr+55);
return a + b + c + d;
}
We currently materialize the constants `3, 7, 23, 39` in registers and use those as index registers with `R3` as the base. However, if we computed the value `r3 + 55`, we can use DQ-Form instructions with displacements (48, 23, 16, 0).
This patch performs these adjustments and fixes up some of the addressing computation functions so as to avoid redundant code.
Repository:
rL LLVM
https://reviews.llvm.org/D65094
Files:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.h
lib/Target/PowerPC/PPCInstr64Bit.td
lib/Target/PowerPC/PPCInstrInfo.td
test/CodeGen/PowerPC/dform-adjust.ll
test/CodeGen/PowerPC/float-load-store-pair.ll
test/CodeGen/PowerPC/peephole-align.ll
test/CodeGen/PowerPC/pre-inc-disable.ll
test/CodeGen/PowerPC/qpx-unal-cons-lds.ll
test/CodeGen/PowerPC/unal-altivec-wint.ll
test/CodeGen/PowerPC/unal-altivec.ll
test/CodeGen/PowerPC/unal-vec-ldst.ll
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