[PATCH] D65063: [PowerPC] Eliminate loads feeding swaps for vector type by using big-endian load.

[Zixuan Wu (Zeson) via Phabricator via llvm-commits]

wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai, jsji.
Herald added subscribers: llvm-commits, shchenz, MaskRay, hiraditya.
Herald added a project: LLVM.

In PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. 
So we can combine vector `load + reverse` into `big endian load` to eliminate the swap instruction. Also combine vector `reverse + store` into `big endian store`.


Repository:
  rL LLVM

https://reviews.llvm.org/D65063

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
  llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll

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