[PATCH] D65024: [GlobalISel][AArch64] Contract trivial same-size cross-bank copies into G_STOREs

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1170
+  assert(I.getOpcode() == TargetOpcode::G_STORE && "Expected G_STORE");
+  // If we're storing 32 bits, it doesn't matter if it's 32 bits on a FPR or a
+  // GPR. So, if we run into something like this:
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You mention 32 bits here but the example uses 64 bit types. Also, it doesn't matter whether we use 32 or 64 bit stores right?


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1184
+  if (!Copy || Copy->getOpcode() != TargetOpcode::COPY)
+    return;
+  Register CopyDstReg = Copy->getOperand(0).getReg();
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This pattern can now be replaced with getOpcodeDef()?


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1276
+  case TargetOpcode::G_STORE:
+    contractCrossBankCopyIntoStore(I, MRI);
+    return false;
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You're returning false here because we want selection to continue, even though you changed the instruction. This is what the preISelLower() hook I added is for.


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  https://reviews.llvm.org/D65024/new/

https://reviews.llvm.org/D65024