[llvm] r366376 - [AMDGPU] Stop special casing flat_scratch for register name

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Wed Jul 17 14:35:11 2019
New Revision: 366376

URL: http://llvm.org/viewvc/llvm-project?rev=366376&view=rev
Log:
[AMDGPU] Stop special casing flat_scratch for register name

Differential Revision: https://reviews.llvm.org/D64885

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td

Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=366376&r1=366375&r2=366376&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Wed Jul 17 14:35:11 2019
@@ -1347,18 +1347,6 @@ void SIRegisterInfo::eliminateFrameIndex
 }
 
 StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
-  // FIXME: Rename flat_scr so we don't need to special case this.
-  switch (Reg) {
-  case AMDGPU::FLAT_SCR:
-    return "flat_scratch";
-  case AMDGPU::FLAT_SCR_LO:
-    return "flat_scratch_lo";
-  case AMDGPU::FLAT_SCR_HI:
-    return "flat_scratch_hi";
-  default:
-    break;
-  }
-
   const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
   unsigned Size = getRegSizeInBits(*RC);
   unsigned AltName = AMDGPU::NoRegAltName;

Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=366376&r1=366375&r2=366376&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Wed Jul 17 14:35:11 2019
@@ -171,7 +171,7 @@ foreach Index = 0-15 in {
 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
   def _ci : SIReg<n, ci_e>;
   def _vi : SIReg<n, vi_e>;
-  def "" : SIReg<"", 0>;
+  def "" : SIReg<n, 0>;
 }
 
 class FlatReg <Register lo, Register hi, bits<16> encoding> :