[llvm] r366340 - AMDGPU: Use getTargetConstant
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 08:35:37 PDT 2019
Author: arsenm
Date: Wed Jul 17 08:35:36 2019
New Revision: 366340
URL: http://llvm.org/viewvc/llvm-project?rev=366340&view=rev
Log:
AMDGPU: Use getTargetConstant
Avoids creating an extra intermediate mov.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp?rev=366340&r1=366339&r2=366340&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp Wed Jul 17 08:35:36 2019
@@ -620,10 +620,10 @@ MachineSDNode *AMDGPUDAGToDAGISel::build
EVT VT) const {
SDNode *Lo = CurDAG->getMachineNode(
AMDGPU::S_MOV_B32, DL, MVT::i32,
- CurDAG->getConstant(Imm & 0xFFFFFFFF, DL, MVT::i32));
+ CurDAG->getTargetConstant(Imm & 0xFFFFFFFF, DL, MVT::i32));
SDNode *Hi =
CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
- CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
+ CurDAG->getTargetConstant(Imm >> 32, DL, MVT::i32));
const SDValue Ops[] = {
CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
Modified: llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll?rev=366340&r1=366339&r2=366340&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/shift-i128.ll Wed Jul 17 08:35:36 2019
@@ -147,13 +147,13 @@ define i128 @v_lshr_i128_kv(i128 %rhs) {
; GCN-LABEL: v_lshr_i128_kv:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s5, 0
-; GCN-NEXT: s_movk_i32 s4, 0x41
-; GCN-NEXT: v_lshr_b64 v[2:3], s[4:5], v0
+; GCN-NEXT: s_mov_b32 s7, 0
+; GCN-NEXT: s_movk_i32 s6, 0x41
+; GCN-NEXT: v_lshr_b64 v[2:3], s[6:7], v0
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v0
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GCN-NEXT: v_mov_b32_e32 v2, 0x41
+; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v2, 0
More information about the llvm-commits
mailing list