[PATCH] D64220: [PowerPC] Remove redundant load immediate instructions

[Yi-Hong Lyu via Phabricator via llvm-commits]

Yi-Hong.Lyu marked an inline comment as done.
Yi-Hong.Lyu added a subscriber: t.p.northover.
Yi-Hong.Lyu added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir:5
+---
+name:            t1
+alignment:       4
----------------
steven.zhang wrote:
> nemanjai wrote:
> > steven.zhang wrote:
> > > Could you show me the LLVM IR that produce these two redundant LI ? So that, we could figure out if they can be avoided instead of removing it in the peephole.
> > More or less any IR that has multiple PHI nodes that have a zero coming in from the same block and the register has to be spilled.
> > Perhaps we should add a test case such as that (with an inline asm call that clobbers registers thereby requiring spills).
> Yeah, at least one case to indicate the scenario that produce this pattern,
There are two test cases in the added remove-redundant-load-imm.ll. The first one only has redundancy on PowerPC, the second one has redundancy for both PowerPC and armv8 (not arm64):

```
$ cat test1.ll
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

define void @hoge(i1 %arg7) {
bb:
  br label %bb10

bb10:                                             ; preds = %bb
  call void @barney.88(i1 %arg7, i32* null)
  ret void
}

declare void @barney.88(i1, i32*)

$ $ $ORI_BIN/llc -O3 -filetype=asm test1.ll -o -
...
# %bb.0:                                # %bb
        mflr 0
        andi. 3, 3, 1
        std 0, 16(1)
        stdu 1, -32(1)
        .cfi_def_cfa_offset 32
        .cfi_offset lr, 16
        li 3, 1
        li 4, 0
        isel 3, 3, 4, 1
        li 4, 0    # redundant load immediate
        bl barney.88
        nop
        addi 1, 1, 32
        ld 0, 16(1)
        mtlr 0
        blr
        .long   0
        .quad   0
...

$ $OPT_BIN/llc -O3 -filetype=asm test1.ll -o -
...
# %bb.0:                                # %bb
        mflr 0
        andi. 3, 3, 1
        std 0, 16(1)
        stdu 1, -32(1)
        .cfi_def_cfa_offset 32
        .cfi_offset lr, 16
        li 3, 1
        li 4, 0
        isel 3, 3, 4, 1
        bl barney.88
        nop
        addi 1, 1, 32
        ld 0, 16(1)
        mtlr 0
        blr
        .long   0
        .quad   0
...
```
```
$ cat test2.ll
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

@global.6 = external global i32*

declare void @barney.94(i8*, i32)

define void @0() {
  store i32* null, i32** @global.6
  call void @barney.94(i8* undef, i32 0)
  unreachable
}

$ $ORI_BIN/llc -O3 -filetype=asm test2.ll -o -
...
# %bb.0:
        mflr 0
        std 0, 16(1)
        stdu 1, -32(1)
        .cfi_def_cfa_offset 32
        .cfi_offset lr, 16
        addis 3, 2, .LC0 at toc@ha
        li 4, 0
        ld 3, .LC0 at toc@l(3)
        std 4, 0(3)
        li 4, 0    # redundant load immediate
        bl barney.94
        nop
        .long   0
        .quad   0
...

$ $OPT_BIN/llc -O3 -filetype=asm test2.ll -o -
...
# %bb.0:
        mflr 0
        std 0, 16(1)
        stdu 1, -32(1)
        .cfi_def_cfa_offset 32
        .cfi_offset lr, 16
        addis 3, 2, .LC0 at toc@ha
        li 4, 0
        ld 3, .LC0 at toc@l(3)
        std 4, 0(3)
        bl barney.94
        nop
        .long   0
        .quad   0
...

$ $ORI_BIN/llc -O3 -mtriple=armv8-eabi -filetype=asm test2.ll -o -
...
@ %bb.0:
        .save   {r11, lr}
        push    {r11, lr}
        movw    r0, :lower16:global.6
        mov     r1, #0
        movt    r0, :upper16:global.6
        str     r1, [r0]
        mov     r1, #0    @ redundant load immediate
        bl      barney.94
...
```

Note.
1. `$ORI_BIN/llc` is the llc without patch and `$OPT_BIN/llc` is the llc with patch. 
2. We are evaluating the feasibility of platform independent implementation as Hal suggested and @t.p.northover for any input


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64220/new/

https://reviews.llvm.org/D64220