[PATCH] D64839: [AMDGPU] Autogenerate register asm names

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:61
+                [ prefix # regNo,
+                  prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
+                  prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]",
----------------
So this generates too many names, and then the extra SGPR ones just don't work?


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:634
 def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
-  (add PRIVATE_RSRC_REG)> {
+  (add PRIVATE_RSRC_REG), Reg32> {
   let isAllocatable = 0;
----------------
This probably shouldn't have a set name, but should be Reg128


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64839/new/

https://reviews.llvm.org/D64839