[PATCH] D64815: [AMDGPU] Change register type for v32 vectors

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: arsenm, kzhuravl, msearles.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely.
arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: test/CodeGen/AMDGPU/v1024.ll:2
+; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}test_v1024:
----------------
Can you add a comment explaining what this tests 


================
Comment at: test/CodeGen/AMDGPU/v1024.ll:8
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
----------------
You can uses GCN-COUNT-<number>


When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.


https://reviews.llvm.org/D64815

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/v1024.ll


Index: test/CodeGen/AMDGPU/v1024.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/v1024.ll
@@ -0,0 +1,58 @@
+; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}test_v1024:
+; GCN-NOT: v_accvgpr
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN: v_mov_b32_e32
+; GCN-NOT: v_accvgpr
+define amdgpu_kernel void @test_v1024() {
+entry:
+  %alloca = alloca <32 x i32>, align 16, addrspace(5)
+  %cast = bitcast <32 x i32> addrspace(5)* %alloca to i8 addrspace(5)*
+  br i1 undef, label %if.then.i.i, label %if.else.i
+
+if.then.i.i:                                      ; preds = %entry
+  call void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* align 16 %cast, i8 addrspace(5)* align 4 undef, i64 128, i1 false)
+  br label %if.then.i62.i
+
+if.else.i:                                        ; preds = %entry
+  br label %if.then.i62.i
+
+if.then.i62.i:                                    ; preds = %if.else.i, %if.then.i.i
+  call void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* align 4 undef, i8 addrspace(5)* align 16 %cast, i64 128, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)
+
+declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -152,8 +152,8 @@
   }
 
   if (Subtarget->hasMAIInsts()) {
-    addRegisterClass(MVT::v32i32, &AMDGPU::AReg_1024RegClass);
-    addRegisterClass(MVT::v32f32, &AMDGPU::AReg_1024RegClass);
+    addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
+    addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
   }
 
   computeRegisterProperties(Subtarget->getRegisterInfo());


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