[PATCH] D54409: PowerPC/SPE: Fix load/store handling for SPE

[Justin Hibbits via Phabricator via llvm-commits]

jhibbits marked an inline comment as done.
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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:2239
+    if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
+      if (Memop->getMemoryVT() == MVT::f64) {
+          Base = N.getOperand(0);
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nemanjai wrote:
> Am I reading this correctly? If this node is used for any memory operation that is accessing an `f64`, we will never use r+i addressing. Is that the desired behaviour?
> 
> So if I'm not mistaken, we have the following semantics:
> - If we are accessing an `MVT::f64`, always use r+r
> - If we are accessing any other type, use r+i if the offset is a 16-bit signed value
>   - Otherwise use r+r addressing
Yes, that's it for right now.  @kthomsen has a fix (commented above), but I wanted to get this in first, and then optimize it after, so @kthomsen's patch will be a separate change.


Repository:
  rL LLVM

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https://reviews.llvm.org/D54409