[PATCH] D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/Xtensa/XtensaRegisterInfo.td:40-45
+def a2 : ARReg<2, "a2">, DwarfRegNum<[2]>;
+def a3 : ARReg<3, "a3">, DwarfRegNum<[3]>;
+def a4 : ARReg<4, "a4">, DwarfRegNum<[4]>;
+def a5 : ARReg<5, "a5">, DwarfRegNum<[5]>;
+def a6 : ARReg<6, "a6">, DwarfRegNum<[6]>;
+def a7 : ARReg<7, "a7">, DwarfRegNum<[7]>;
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Usually the register names and corresponding generated enums are capitalized


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64830/new/

https://reviews.llvm.org/D64830