[PATCH] D56703: PowerPC: Fix register spilling for SPE registers

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.
Herald added subscribers: wuzish, MaskRay.

LGTM other than the code here looks really messy - but it looks messy regardless of this patch.

I think after this lands, we should refactor this stuff to something like this:

  const MCPhysReg *CSRLists[] = {
    CSR_64_AllRegs_VSX_SaveList,
    CSR_64_AllRegs_Altivec_SaveList,
    CSR_64_AllRegs_SaveList,
    CSR_Darwin64_Altivec_SaveList,
    CSR_Darwin64_SaveList,
    CSR_Darwin32_Altivec_SaveList,
    CSR_Darwin32_SaveList,
    ...
  };
  
  // Compute the index into the array based on Subtarget features, calling convention, ABI, the need to save R2, and object mode (32/64 bit).
  return CSRLists[ComputedIdx];

and similarly for the regmasks.



================
Comment at: lib/Target/PowerPC/PPCRegisterInfo.cpp:170
+                      : CSR_SVR64_ColdCC_Altivec_SaveList;
+      else
+        return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
----------------
No need for `else` when the previous `if` just does a `return`. The same comment applies to all the `else` statements here.
```
// Cold calling convention CSR's.
if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
  // 64-bit targets.
  if (TM.isPPC64()) {
    if (Subtarget.hasAltivec())
      return SaveR2 ? ...
    return SaveR2 ? ...
  }
  // 32-bit targets.
  if (Subtarget.hasAltivec())
    return CSR_SVR32_ColdCC_Altivec_SaveList;
  if (Subtarget.hasSPE())
    return CSR_SVR32_ColdCC_SPE_SaveList;
  return CSR_SVR32_ColdCC_SaveList
}

// Standard calling convention CSR's.
...
```


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56703/new/

https://reviews.llvm.org/D56703