[llvm] r366254 - AMDGPU/GlobalISel: Select G_SHL
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 13:15:30 PDT 2019
Author: arsenm
Date: Tue Jul 16 13:15:30 2019
New Revision: 366254
URL: http://llvm.org/viewvc/llvm-project?rev=366254&view=rev
Log:
AMDGPU/GlobalISel: Select G_SHL
I think this manages to not break the DAG handling with the divergent
predicates because the stadalone divergent patterns end up with a
higher priority than the pattern on the instruction definition.
The 16-bit versions don't work yet.
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=366254&r1=366253&r2=366254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Tue Jul 16 13:15:30 2019
@@ -511,10 +511,10 @@ let AddedComplexity = 1 in {
let Defs = [SCC] in {
// TODO: b64 versions require VOP3 change since v_lshlrev_b64 is VOP3
def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
- [(set i32:$sdst, (UniformBinFrag<shl> i32:$src0, i32:$src1))]
+ [(set SReg_32:$sdst, (shl (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
- [(set i64:$sdst, (UniformBinFrag<shl> i64:$src0, i32:$src1))]
+ [(set SReg_64:$sdst, (shl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
[(set i32:$sdst, (UniformBinFrag<srl> i32:$src0, i32:$src1))]
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=366254&r1=366253&r2=366254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Tue Jul 16 13:15:30 2019
@@ -474,7 +474,7 @@ defm V_MIN_U32 : VOP2Inst <"v_min_u32",
defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">;
defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
-defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">;
+defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=366254&r1=366253&r2=366254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Tue Jul 16 13:15:30 2019
@@ -393,7 +393,7 @@ def V_MULLIT_F32 : VOP3Inst <"v_mullit_f
} // End SubtargetPredicate = isGFX6GFX7GFX10, Predicates = [isGFX6GFX7GFX10]
let SubtargetPredicate = isGFX8Plus in {
-def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
+def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
} // End SubtargetPredicate = isGFX8Plus
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir?rev=366254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir Tue Jul 16 13:15:30 2019
@@ -0,0 +1,327 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
+
+---
+name: shl_s32_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: shl_s32_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX6: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ ; GFX7-LABEL: name: shl_s32_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX7: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX7: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ ; GFX8-LABEL: name: shl_s32_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX8: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ ; GFX9-LABEL: name: shl_s32_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX9: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ ; GFX10-LABEL: name: shl_s32_ss
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX10: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX10: S_ENDPGM 0, implicit [[S_LSHL_B32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s32) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s32_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_s32_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX7-LABEL: name: shl_s32_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX8-LABEL: name: shl_s32_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX9-LABEL: name: shl_s32_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX10-LABEL: name: shl_s32_sv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s32) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s32_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_s32_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX7-LABEL: name: shl_s32_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX8-LABEL: name: shl_s32_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX9-LABEL: name: shl_s32_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX10-LABEL: name: shl_s32_vs
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s32) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: shl_s32_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX7-LABEL: name: shl_s32_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX7: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX8-LABEL: name: shl_s32_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX9-LABEL: name: shl_s32_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ ; GFX10-LABEL: name: shl_s32_vv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s64_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; GFX6-LABEL: name: shl_s64_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX6: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
+ ; GFX7-LABEL: name: shl_s64_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX7: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX7: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
+ ; GFX8-LABEL: name: shl_s64_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX8: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
+ ; GFX9-LABEL: name: shl_s64_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX9: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX9: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
+ ; GFX10-LABEL: name: shl_s64_ss
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX10: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX10: S_ENDPGM 0, implicit [[S_LSHL_B64_]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s32) = COPY $sgpr2
+ %2:sgpr(s64) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s64_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $vgpr0
+ ; GFX6-LABEL: name: shl_s64_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX7-LABEL: name: shl_s64_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX8-LABEL: name: shl_s64_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX9-LABEL: name: shl_s64_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX10-LABEL: name: shl_s64_sv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s64) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s64_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0_vgpr1
+ ; GFX6-LABEL: name: shl_s64_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX7-LABEL: name: shl_s64_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX8-LABEL: name: shl_s64_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX9-LABEL: name: shl_s64_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX10-LABEL: name: shl_s64_vs
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s64) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_s64_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX6-LABEL: name: shl_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX7-LABEL: name: shl_s64_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX7: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX8-LABEL: name: shl_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX8: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX9-LABEL: name: shl_s64_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ ; GFX10-LABEL: name: shl_s64_vv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_LSHLREV_B64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(s64) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir?rev=366254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir Tue Jul 16 13:15:30 2019
@@ -0,0 +1,203 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX8 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX8,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# ERR-NOT: remark
+# ERR-GFX8: remark: <unknown>:0:0: cannot select: %3:sgpr(s16) = G_SHL %2:sgpr, %1:sgpr(s32) (in function: shl_s16_ss)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:sgpr, %1:vgpr(s32) (in function: shl_s16_sv)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:sgpr(s32) (in function: shl_s16_vs)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:vgpr(s32) (in function: shl_s16_vv)
+
+# ERR-GFX910: remark: <unknown>:0:0: cannot select: %3:sgpr(s16) = G_SHL %2:sgpr, %1:sgpr(s32) (in function: shl_s16_ss)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:sgpr, %1:vgpr(s32) (in function: shl_s16_sv)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:sgpr(s32) (in function: shl_s16_vs)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_SHL %2:vgpr, %1:vgpr(s32) (in function: shl_s16_vv)
+
+# ERR-NOT: remark
+
+---
+name: shl_s16_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: shl_s16_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX6: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX7-LABEL: name: shl_s16_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX7: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX8-LABEL: name: shl_s16_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX9-LABEL: name: shl_s16_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX10-LABEL: name: shl_s16_ss
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX10: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[SHL:%[0-9]+]]:sgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](s16)
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s16) = G_TRUNC %0
+ %3:sgpr(s16) = G_SHL %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: shl_s16_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_s16_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX7-LABEL: name: shl_s16_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX8-LABEL: name: shl_s16_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX9-LABEL: name: shl_s16_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX10-LABEL: name: shl_s16_sv
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](s16)
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:sgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_SHL %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: shl_s16_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_s16_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX7-LABEL: name: shl_s16_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX8-LABEL: name: shl_s16_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX9-LABEL: name: shl_s16_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX10-LABEL: name: shl_s16_vs
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](s16)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_SHL %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: shl_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: shl_s16_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX6: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX7-LABEL: name: shl_s16_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX7: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX8-LABEL: name: shl_s16_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX9-LABEL: name: shl_s16_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](s16)
+ ; GFX10-LABEL: name: shl_s16_vv
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX10: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](s16)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_SHL %2, %1
+ S_ENDPGM 0, implicit %3
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir?rev=366254&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir Tue Jul 16 13:15:30 2019
@@ -0,0 +1,168 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# ERR-NOT: remark
+# ERR-GFX910: remark: <unknown>:0:0: cannot select: %2:sgpr(<2 x s16>) = G_SHL %0:sgpr, %1:sgpr(<2 x s16>) (in function: shl_v2s16_ss)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_SHL %0:sgpr, %1:vgpr(<2 x s16>) (in function: shl_v2s16_sv)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_SHL %0:vgpr, %1:sgpr(<2 x s16>) (in function: shl_v2s16_vs)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_SHL %0:vgpr, %1:vgpr(<2 x s16>) (in function: shl_v2s16_vv)
+# ERR-NOT: remark
+
+---
+name: shl_v2s16_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: shl_v2s16_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX6: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX7-LABEL: name: shl_v2s16_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX7: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX8-LABEL: name: shl_v2s16_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX8: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX9-LABEL: name: shl_v2s16_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX9: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX10-LABEL: name: shl_v2s16_ss
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX10: [[SHL:%[0-9]+]]:sgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<2 x s16>) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_v2s16_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_v2s16_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX7-LABEL: name: shl_v2s16_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX8-LABEL: name: shl_v2s16_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX9-LABEL: name: shl_v2s16_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX10-LABEL: name: shl_v2s16_sv
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr0
+ %2:vgpr(<2 x s16>) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_v2s16_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: shl_v2s16_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX7-LABEL: name: shl_v2s16_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX8-LABEL: name: shl_v2s16_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX9-LABEL: name: shl_v2s16_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX10-LABEL: name: shl_v2s16_vs
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr0
+ %2:vgpr(<2 x s16>) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: shl_v2s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: shl_v2s16_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX6: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX7-LABEL: name: shl_v2s16_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX7: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX8-LABEL: name: shl_v2s16_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX8: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX9-LABEL: name: shl_v2s16_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX9: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ ; GFX10-LABEL: name: shl_v2s16_vv
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX10: [[SHL:%[0-9]+]]:vgpr(<2 x s16>) = G_SHL [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[SHL]](<2 x s16>)
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<2 x s16>) = G_SHL %0, %1
+ S_ENDPGM 0, implicit %2
+...
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