[llvm] r366252 - [AMDGPU] Change register type for v32 vectors

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Tue Jul 16 13:06:00 2019
New Revision: 366252

URL: http://llvm.org/viewvc/llvm-project?rev=366252&view=rev
Log:
[AMDGPU] Change register type for v32 vectors

When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.

Differential Revision: https://reviews.llvm.org/D64815

Added:
    llvm/trunk/test/CodeGen/AMDGPU/v1024.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=366252&r1=366251&r2=366252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Jul 16 13:06:00 2019
@@ -152,8 +152,8 @@ SITargetLowering::SITargetLowering(const
   }
 
   if (Subtarget->hasMAIInsts()) {
-    addRegisterClass(MVT::v32i32, &AMDGPU::AReg_1024RegClass);
-    addRegisterClass(MVT::v32f32, &AMDGPU::AReg_1024RegClass);
+    addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
+    addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
   }
 
   computeRegisterProperties(Subtarget->getRegisterInfo());

Added: llvm/trunk/test/CodeGen/AMDGPU/v1024.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/v1024.ll?rev=366252&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/v1024.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/v1024.ll Tue Jul 16 13:06:00 2019
@@ -0,0 +1,29 @@
+; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; Check that we do not use AGPRs for v32i32 type
+
+; GCN-LABEL: {{^}}test_v1024:
+; GCN-NOT: v_accvgpr
+; GCN-COUNT-32: v_mov_b32_e32
+; GCN-NOT: v_accvgpr
+define amdgpu_kernel void @test_v1024() {
+entry:
+  %alloca = alloca <32 x i32>, align 16, addrspace(5)
+  %cast = bitcast <32 x i32> addrspace(5)* %alloca to i8 addrspace(5)*
+  br i1 undef, label %if.then.i.i, label %if.else.i
+
+if.then.i.i:                                      ; preds = %entry
+  call void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* align 16 %cast, i8 addrspace(5)* align 4 undef, i64 128, i1 false)
+  br label %if.then.i62.i
+
+if.else.i:                                        ; preds = %entry
+  br label %if.then.i62.i
+
+if.then.i62.i:                                    ; preds = %if.else.i, %if.then.i.i
+  call void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* align 4 undef, i8 addrspace(5)* align 16 %cast, i64 128, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)
+
+declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)