[PATCH] D64174: [DAGCombine] Do several rounds of combine for addcarry nodes.

Tue Jul 16 10:04:45 PDT 2019

RKSimon added inline comments.

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Comment at: test/CodeGen/X86/addcarry.ll:326
+; CHECK-NEXT:    adcq %rdi, %rbx
+; CHECK-NEXT:    addq %r10, %rdx
+; CHECK-NEXT:    adcq %rdi, %rcx
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craig.topper wrote:
> RKSimon wrote:
> > deadalnix wrote:
> > > craig.topper wrote:
> > > > Doesn't this add and adc compute the same result as line 321 and 325?
> > > There is a lot of duplication that is generated by this. But once the carry propagation is "linearized" because you removed all the diamonds, then a simple set of optimization can get rid of it all. See D57317 for that specific case.
> > Would adding X86ISD::ADD to X86TargetLowering::isCommutativeBinOp help with this?
> If I remember right from what I saw in the DAG. We need to CSE ISD::ADDCARRY with commuted operands in DAG combine. Not sure about the X86ISD node.
By the looks of this, DAGCombiner::combine should handle it - but is disabled for commutative binop nodes with more than 1 output value.....

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64174/new/

https://reviews.llvm.org/D64174