[PATCH] D64807: AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 09:59:58 PDT 2019
nhaehnle created this revision.
nhaehnle added reviewers: rampitec, mareko.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630
Repository:
rL LLVM
https://reviews.llvm.org/D64807
Files:
lib/Target/AMDGPU/GCNHazardRecognizer.cpp
test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
Index: test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
===================================================================
--- test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
+++ test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
@@ -92,6 +92,7 @@
...
# GCN-LABEL: name: vmem_write_exec_impread
# GCN: BUFFER_LOAD_DWORD_OFFEN
+# GCN: V_NOP
# GCN-NEXT: S_MOV_B64
---
name: vmem_write_exec_impread
@@ -208,3 +209,16 @@
$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, implicit $exec
S_BRANCH %bb.0
...
+# GCN-LABEL: name: ds_write_exec
+# GCN: DS_WRITE_B32_gfx9
+# GCN-NEXT: V_NOP
+# GCN-NEXT: S_MOV_B32
+---
+name: ds_write_exec
+body: |
+ bb.0:
+ $vgpr0 = IMPLICIT_DEF
+ $vgpr1 = IMPLICIT_DEF
+ DS_WRITE_B32_gfx9 $vgpr0, $vgpr1, 0, 0, implicit $exec
+ $exec_lo = S_MOV_B32 -1
+...
Index: lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -920,7 +920,7 @@
for (const MachineOperand &Def : MI->defs()) {
MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
- if (!Op || (Op->isImplicit() && Op->getReg() == AMDGPU::EXEC))
+ if (!Op)
continue;
return true;
}
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